I'm using a bittware board with VU9P on it. The integrated pcie IP synthesizes fine, and the card shows up in lspci. However I do not receive any data on the m_axis_cq interface. The valid bit never goes high, and the data line does not toggle. I'm using a very similar sw code from my ultrascale setup, so I'm confident about the software side.
Unfortunately it's more and more looking like a synthesis/hard logic bug. I'm using Vivado 2017.1. I've narrowed it down to the BAR I'm sending the data to. I have two 32-bit bars, and two 64-bit prefetchable bars. The data shows up when I send it to 32-bit bars, but not when I send it to the 64-bit bars.