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Observer
Observer
10,273 Views
Registered: ‎02-01-2014

PCIe on VC709: Convert AXIS to AXIMM

My apologies if there are similar posts or an application note that I've missed. I've been reading up on this for a couple days now and still don't have a good feeling for how to tackle this problem. I know it can be done, but I'm hoping for a nudge in the right direction, so I can focus my efforts.

 

Basically, what I'm looking for is a simple way to convert the AXIS interfaces found on the PCIe IP into memory mapped AXI in order to pass data to/from the SDRAM.

 

What I'm really looking for is this: http://www.xilinx.com/support/documentation/ip_documentation/axi_pcie/v2_1/pg055-axi-bridge-pcie.pdf, but that's not available for the Virtex 7 690T found on the VC709. Is that right? Any way to use it on the VC709 FPGA?

 

I've been looking at the virtual FIFO - is that the way to go? I've also been going through the TRD (http://www.xilinx.com/products/boards-and-kits/EK-V7-VC709-CES-G.htm) code and trying to replicate their PCIe to Memory setup. I'm not looking to use the Northwest Logic DMA core at this time - will that cause any issues?

 

Thank you for all the help,

Bryan

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Observer
Observer
10,264 Views
Registered: ‎02-01-2014

Re: PCIe on VC709: Convert AXIS to AXIMM

I should also mention that I was planning to expose the SDRAM as one of the PCIe BARs. I wanted another BAR set up that referenced memory (registers) internal to the FPGA, so that a host can read/write data to various AXI peripherals inside the FPGA in addition to SDRAM.

 

Bryan

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Explorer
Explorer
10,212 Views
Registered: ‎12-06-2013

Re: PCIe on VC709: Convert AXIS to AXIMM

Xilinx put this on their roadmap for 2014 (sorry, I don't have the link) but for now you will have to build it yourself.

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Explorer
Explorer
10,211 Views
Registered: ‎12-06-2013

Re: PCIe on VC709: Convert AXIS to AXIMM

I apologize, just realized I didn't answer your question. You will have to create a BAR writer and a BAR completer that separates address control signals from read/write control signals. For a single MM master you will have to send your writes on while diverting your reads in MM reads and apply the PCIe completion rules and pg023 guidlines as well. I won't say this is an task that is done quickly but it certainly is doable. The best way to start this is by writing a component for each process, i.e. write data (posted TLPs).

 

While doing this split the packets up into read address, write address and write data. For a single BAR this should be fairly straight forward for writes. Once you get this far you will have a better understanding of how the completions should work which is most likely where you would spend most of your time.

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