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Anonymous
Not applicable
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PCIe place and route problem

Hello,

 

I have a design with 2 AXI Bridge PCIe Gen3 Root Port 4 lanes configuration.

 

I tested 2 configurations to implement my design:

 

1-  I use advanced mode in the IP configuration. Then I select GTH Quad 226 for the first and GTH Quad 225 for the second. The placement done without errors or worning.

 

2- I use advanced mode in the IP configuration. Then I select GTH Quad 224 for the first and GTH Quad 223 for the second I had these critical wornings:

 

 

[Vivado 12-2285] Cannot set LOC property of instance 'design_1_i/xdma_1/inst/pcie4_ip_i/inst/pcie_4_0_pipe_inst/pcie_4_0_e4_inst'... Instance design_1_i/xdma_1/inst/pcie4_ip_i/inst/pcie_4_0_pipe_inst/pcie_4_0_e4_inst can not be placed in PCIE40E4 of site PCIE40E4_X0Y0 because the bel is occupied by design_1_i/xdma_0/inst/pcie4_ip_i/inst/pcie_4_0_pipe_inst/pcie_4_0_e4_inst(port:). This could be caused by bel constraint conflict ["/.../sources_1/bd/design_1/ip/design_1_xdma_0_1/ip_0/source/ip_pcie4_uscale_plus_x0y0.xdc":114]


[Vivado 12-2285] Cannot set LOC property of instance 'design_1_i/xdma_1/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_xdma_0_1_pcie4_ip_gt_i/inst/gen_gtwizard_gthe4_top.design_1_xdma_0_1_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[3].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST'... Instance design_1_i/xdma_1/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_xdma_0_1_pcie4_ip_gt_i/inst/gen_gtwizard_gthe4_top.design_1_xdma_0_1_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[3].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y15 because the bel is occupied by design_1_i/xdma_0/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gthe4_top.design_1_xdma_0_0_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[3].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST(port:). This could be caused by bel constraint conflict ["/.../sources_1/bd/design_1/ip/design_1_xdma_0_1/ip_0/ip_0/synth/design_1_xdma_0_1_pcie4_ip_gt.xdc":120]


[Vivado 12-2285] Cannot set LOC property of instance 'design_1_i/xdma_1/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_xdma_0_1_pcie4_ip_gt_i/inst/gen_gtwizard_gthe4_top.design_1_xdma_0_1_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[3].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST'... Instance design_1_i/xdma_1/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_xdma_0_1_pcie4_ip_gt_i/inst/gen_gtwizard_gthe4_top.design_1_xdma_0_1_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[3].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y14 because the bel is occupied by design_1_i/xdma_0/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gthe4_top.design_1_xdma_0_0_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[3].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST(port:). This could be caused by bel constraint conflict ["/.../sources_1/bd/design_1/ip/design_1_xdma_0_1/ip_0/ip_0/synth/design_1_xdma_0_1_pcie4_ip_gt.xdc":99]


[Vivado 12-2285] Cannot set LOC property of instance 'design_1_i/xdma_1/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_xdma_0_1_pcie4_ip_gt_i/inst/gen_gtwizard_gthe4_top.design_1_xdma_0_1_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[3].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST'... Instance design_1_i/xdma_1/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_xdma_0_1_pcie4_ip_gt_i/inst/gen_gtwizard_gthe4_top.design_1_xdma_0_1_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[3].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y13 because the bel is occupied by design_1_i/xdma_0/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gthe4_top.design_1_xdma_0_0_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[3].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST(port:). This could be caused by bel constraint conflict ["/.../sources_1/bd/design_1/ip/design_1_xdma_0_1/ip_0/ip_0/synth/design_1_xdma_0_1_pcie4_ip_gt.xdc":78]


[Vivado 12-2285] Cannot set LOC property of instance 'design_1_i/xdma_1/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_xdma_0_1_pcie4_ip_gt_i/inst/gen_gtwizard_gthe4_top.design_1_xdma_0_1_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[3].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST'... Instance design_1_i/xdma_1/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_xdma_0_1_pcie4_ip_gt_i/inst/gen_gtwizard_gthe4_top.design_1_xdma_0_1_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[3].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y12 because the bel is occupied by design_1_i/xdma_0/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gthe4_top.design_1_xdma_0_0_pcie4_ip_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[3].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST(port:). This could be caused by bel constraint conflict ["/.../sources_1/bd/design_1/ip/design_1_xdma_0_1/ip_0/ip_0/synth/design_1_xdma_0_1_pcie4_ip_gt.xdc":57]

 

 

Why the placement with the first configuration is done correctly and it is failed in the second?

 

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7 Replies
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Mentor
Mentor
1,365 Views
Registered: ‎02-24-2014

Because you are trying to put 2 different PCIe interfaces in the same location:

 

Then I select GTH Quad 224 for the first and GTH Quad 224

Don't forget to close a thread when possible by accepting a post as a solution.
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Anonymous
Not applicable
1,342 Views

Hello @jmcclusk,

 

sorry, it's a typo.

 

I mean that the GTH Quad 224 is selected for the first one and GTH Quad 223 is selected for the second. And I had the previous warning.

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Mentor
Mentor
1,332 Views
Registered: ‎02-24-2014

Well, according to the error messages, you are placing different PCIe cores into the same location, which is clearly impossible.

 

Dig into the XDC files to see why.

"/.../sources_1/bd/design_1/ip/design_1_xdma_0_1/ip_0/source/ip_pcie4_uscale_plus_x0y0.xdc":114

 

It looks like you'll have to experiment with the IP core to get things in the right place.

Don't forget to close a thread when possible by accepting a post as a solution.
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Moderator
Moderator
1,285 Views
Registered: ‎02-16-2010

In your two tests, can you check the PCIe block locations option selected in the GUI?

For the failing case, whether the PCIe block location option is same for both the IP instances?
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Anonymous
Not applicable
1,278 Views

Hello,

I inderstand why I had this problem:

I sepecified the PCIe blocks locations in the IP GUI and in the xdc file.

When I remove the PCIe assignment constraint from the xdc, the PCIe blocks are routed correctly in the locations specified in the GUI.

Why we must not define the PCIe locations in the xdc constraint file ?

 

 

 

 

 

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Moderator
Moderator
1,264 Views
Registered: ‎02-16-2010

Can you provide exact details of your observation? Please provide the location you specified in the GUI and the xdc constraint used.
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Mentor
Mentor
1,262 Views
Registered: ‎02-24-2014

Because the PCIe IP has it's own constraint file.     This is not always easy to see, but it's there.    Duplicating the constraints in your main XDC file is not needed, and can cause problems, as you have found.

Don't forget to close a thread when possible by accepting a post as a solution.