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zhikai
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Participant
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Registered: ‎07-10-2018

PCIe sys_clk port selection about 7 series FPGA

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When I opened the pcie3_7x_0_qpll_wrapper.v in the PCIe core, I found the QPLLREFCLKSEL port of the GTXE2_COMMON primitive is a constant 3'd1, which means that GTREFCLK0 is selected as the input reference clock to the QPLL according to ug476.

So I want to know whether I can use the MGTREFCLK1P/MGTREFCLK1n pins in the same GTX Quad ? Or do I have to use the MGTREFCLK0P/MGTREFCLK0n pins as the sys_clk in the PCIe core?

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coryb
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Registered: ‎02-11-2014

Hello @zhikai,

You can select MGTREFCLK0 or MGTREFCLK1 for your pinout of sysclk. Both are supported. GTXE2_COMMON will always use the GTREFLK0 port within the IP no matter what MGTREFCLK you decide to use in that quad.

Thanks,
Cory

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coryb
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Registered: ‎02-11-2014

Hello @zhikai,

You can select MGTREFCLK0 or MGTREFCLK1 for your pinout of sysclk. Both are supported. GTXE2_COMMON will always use the GTREFLK0 port within the IP no matter what MGTREFCLK you decide to use in that quad.

Thanks,
Cory

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zhikai
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Registered: ‎07-10-2018
Thank you @coryb, I'll try it.
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