cancel
Showing results for 
Search instead for 
Did you mean: 
Participant
Participant
687 Views
Registered: ‎02-28-2018

PCIe to AXI-MM Core BAR Space Map Problem

Hi, everyone!

I use PCIe to AXI-MM core on Artix 7 FPGA. I choose BAR0 and BAR2 in GUI, but when I use WinDriver debug my card, there are BAR0 and BAR1, do not BAR0 and BAR2; When I choose BAR0, BA1 and BAR2 in GUI, they all appear on WinDriver.

Is it mean that I have to always choosing   BAR1? If no, could someone tell me what incorrect operation I do?

Thanks very much!

0 Kudos
1 Reply
Highlighted
Moderator
Moderator
640 Views
Registered: ‎02-16-2010

Re: PCIe to AXI-MM Core BAR Space Map Problem

Is there a reason to chose BAR0 and BAR2 and skip BAR1?

In Type0 configuration space (Table 2-24 of PG054), the BAR1 address is next to BAR0 address. It could be that BIOS/OS is reading this address space sequentially unless there is a pointer to the next capability which is present on address 34h.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------