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Participant daowen
Participant
667 Views
Registered: ‎02-28-2018

PCIe to AXI-MM Core BAR Space Map Problem

Hi, everyone!

I use PCIe to AXI-MM core on Artix 7 FPGA. I choose BAR0 and BAR2 in GUI, but when I use WinDriver debug my card, there are BAR0 and BAR1, do not BAR0 and BAR2; When I choose BAR0, BA1 and BAR2 in GUI, they all appear on WinDriver.

Is it mean that I have to always choosing   BAR1? If no, could someone tell me what incorrect operation I do?

Thanks very much!

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1 Reply
Moderator
Moderator
620 Views
Registered: ‎02-16-2010

Re: PCIe to AXI-MM Core BAR Space Map Problem

Is there a reason to chose BAR0 and BAR2 and skip BAR1?

In Type0 configuration space (Table 2-24 of PG054), the BAR1 address is next to BAR0 address. It could be that BIOS/OS is reading this address space sequentially unless there is a pointer to the next capability which is present on address 34h.
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