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Registered: ‎05-19-2017

PCIe to DDR DMA on XCVU9P

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I am doing bringup of a VCU118 and I attempted to bridge the PCIe and MIG. The attempt to do this manually failed with a timing violation inside of the Xilinx PCIe IP core. The source and destination of one of these timing violations is as below:

 

  • vcu118_pcie_x16_gen3_i/inst/pcie_4_0_pipe_inst/pcie_4_0_init_ctrl_inst/cfg_phy_link_down_user_clk_o_reg/C
  • vcu118_pcie_x16_gen3_i/inst/pcie_4_0_pipe_inst/pcie4_0_512b_intfc_mod/pcie_4_0_512b_intfc_int_mod/pcie_4_0_512b_rq_intfc_mod/pcie_4_0_512b_async_fifo_blk/read_ptr_reg[1]_rep/R

Looking at the area usage in the implemented view, one thing that is clear is that the PCIe PHY is really, really far from where the MIG pins are, so the logic is trailing halfway across the chip.

 

I then attempted to use Xilinx DMA/Bridge Subsystem for PCIe and hooking it up to the MIG via an AXI interconnect in a block design to see if it's just a problem with my bridging. Except, that also failed timing.

 

The above being the case, I feel the need to ask. Is it even possible to do PCIe to MIG DMA on the VCU118?

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Registered: ‎05-19-2017

So answering my own question, there are two memory channels on the VCU118 board, C1 and C2. Attempting to connect C2 to the PCIe interface results in the timing failure, while C1 can be connected and still meet timing using Xilinx's own DMA engine. So this seems to indicate that the C2 memory is not reachable by the PCIe logic.

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Registered: ‎05-19-2017

So answering my own question, there are two memory channels on the VCU118 board, C1 and C2. Attempting to connect C2 to the PCIe interface results in the timing failure, while C1 can be connected and still meet timing using Xilinx's own DMA engine. So this seems to indicate that the C2 memory is not reachable by the PCIe logic.

View solution in original post

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