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Adventurer
Adventurer
7,690 Views
Registered: ‎07-12-2012

PCIe transfer time is too large

Hi everyone,

 

I have implemented a RootComplex - EndPoint system with two cores of Xilinx. I have modified them in order to write and read data of more than 1 byte, since the original cores are not capable of it. I have done it succesfully, and both cores write and read words of 128 bytes.

 

My problem is as follows: in my initial estimations, I obtained that I would need 0.3 us to write 128-bytes data @5GT/s (I can detail this estimation if someone asks for it). However, when simulating my RC-EP system, I obtain a 128-bye data transfer time of aprox. 3us (@5GT/s) between the beginning of the TLP write and the end of  the TLP receipt. I just don't know why I do have this difference between both times. 

 

datatransfer128bytes5gts.jpg

 

Can somebody help me?

 

Regards,

Alberto.

 

 

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Adventurer
Adventurer
7,673 Views
Registered: ‎07-12-2012

Re: PCIe transfer time is too large

I have been implementing the RC-EP system given by Xilinx when generating an EndPoint core, and I have checked that, when sending many consecutive write commands (payload = 1 DW):

 

- there is about 0.5 us between sending every request and its reception at the EP.

 

- but between every command there is just an interval of a few nanoseconds, that is, the estimated time is maintained between them.

 

writecommands1DW_5gts.jpg

 

It looks like there is a propragation time, ineherent to the device, but I am not sure about this, and I also don't understand it. Can someone talk me more about any of these issues?

 

Thank you in advance,

Alberto.

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