01-31-2018 10:48 AM
Attached is the logic analyser scope traces of our PCIe EP when we power up. I am trying to configure ILA's to trigger and capture more data at startup but this is good enough for this discussion. When started to see an issue with interfacing to our PCIe interface when starting up. Initial read requests after power up returned xffffffff and we would have to reboot the system to get a valid read. later we found that if we removed the device, reset, and rescaned the PCIe we could recover.
Looking for root cause on why we were seeing this turned up that tx_tready out of the PCIe core is low after power up. Later in the scope shots attached we see that it does come up but a cfg_message_received flag seams to result in it falling and never recovering. Any ideas on why this happens and why the resulting system looks fine in all aspects except the tx_tready being low?
Vivado 2014.3.1, 7 series Kintex FPGA
02-08-2018 03:01 AM
Have you checked that the FPGA Configuration has been completed before PERST# releases?
02-21-2018 02:31 PM
Not familure with PERST# in this system. Configuration is completed and then the processor is released from reset. The reset to the PCIe core is active untill we see the processor come up and then we see it configure and link during bios (<200us) then we get a cfg_mgs_recieved flag, then tready goes low. Nothing in the status bits about power management configuration message received but now it looks like that must be happening. Thinking the bios is putting the PCIe core in power saving mode but don't know how to undo or stop that from happening. Any other reasons tready would go low?
02-22-2018 10:25 PM
Do you know what message was received when the link goes to be down?