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grs
Xilinx Employee
Xilinx Employee
5,151 Views
Registered: ‎04-16-2008

PCIe v1.9.4 trn_lnk_up_n takes longer to assert in simulation.

When I simulate PCIe v1.9.4 x1 it takes about 249 us to assert. Is this right?
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3 Replies
kbandekar
Visitor
Visitor
3,868 Views
Registered: ‎01-20-2011

Hi,

 

PCI -e is generated through Xilinx core generator s6_pcie_v1_4.

 

I am using the SP605 board and using the Isim M.81d to simulate the pci-e core.

 

Firstly my simulations are too slow.

I would like to know if trn_lnk_up_n should always be high/ Do I have to run the simulations for couple of hours to see the trn_lnk_up_n going low.

 

What are the conditions for the trn_lnk_up_n to go low ?

 

cheers,

Kunal

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jayer
Xilinx Employee
Xilinx Employee
3,862 Views
Registered: ‎08-07-2007

Hi,

 

trn_lnk_up_n should go low in about 40-50 microseconds. If it is not then something is wrong. This signal going low indicates the link is trained and in L0. Have you compiled your libraries for MTI? For informaiton on how to do this the synthesis and simulation ug:

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/sim.pdf

 

Other things to look for is to ensure the clock frequency feeding the core is right. That the reset is released. Check that trn_reset_n is going from low to high.  

 

-John

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luisb
Xilinx Employee
Xilinx Employee
3,857 Views
Registered: ‎04-06-2010

Hi Kunal,

 

ISim may take a long time for trn_lnk_up_n to assert.  I would look at the ISIM user guide to see if there are any optimization options you have to make this go faster.  I would also check if you have the full version of ISIM.  I know there's a lite version that can go pretty slow after a certain amount of delta cycles.  If you want to make sure you're making progress, pull in the ltssm output of the core to make sure you're on your way to L0.

 

Hope this helps...

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