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Visitor
Visitor
2,514 Views
Registered: ‎05-19-2017

PIPE Mode Simulation of Ultrascale Gen3 PCIe Endpoint Block (v4.3) fails

Hi,

 

I am struggling with the PIPE Mode Simulation option using the Ultrascale Gen3 PCIe Endpoint Block (v4.3) in Vivado 2017.1

 

I would like to speed up simulation of my PCIe application using PIPE Mode Simulation as stated in PG156 page 229 but I can't get the PCIe link up when using the PIPE mode simulation option. "Normal" Simulation with transceivers works fine.

For reference I started the simulation in the example design of the IP to compare my set up with the example design. But the simulation in the example design does not run either.

After the system reset becomes de-asserted there are no more events in the example simulation:


[             4995000] : System Reset Is De-asserted...
run: Time (s): cpu = 00:00:46 ; elapsed = 00:17:34 . Memory (MB): peak = 921.070 ; gain = 0.000

 

Do I miss something out when configuring the IP-Core?

 

The only change I made was activating 'Enable External PIPE Interface' in the Customization GUI of the IP-Block.

 

Further, I can't find the mentioned files (xil_sig2pipe.v and phy_sig_gen.v PG156 page 229) in the IP folder.

 

 

Any help on this is much appreciated.

 

Kind regards,

Mark

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Xilinx Employee
Xilinx Employee
2,429 Views
Registered: ‎08-02-2007

The fast link training can be achieved by set the parameter in the top level

  parameter PL_SIM_FAST_LINK_TRAINING = "TRUE",

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Visitor
Visitor
2,424 Views
Registered: ‎05-19-2017

Looks like the parameter PL_SIM_FAST_LINK_TRAINING is already set to TRUE. I checked both the endpoint and rootport core modules in the example design with ISIM. But the link does not come up

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Xilinx Employee
Xilinx Employee
2,235 Views
Registered: ‎12-10-2013

Hi Mark,

 

The two files you mentioned will be generated, but only show up in the SIM sources, rather than the main IP sources, and I believe will only be generated with the example design.

 

I recommend opening the example design with this, and utilizing the instantiation template in the board.v files.  This will provide both the Xilinx RP, and a 3rd party RP instantiation template, along with many notes on requirements for PIPE mode.  This will also create the xil_sig2pipe.v - which will allow a more convenient naming convention.  Often times we see the below because there is an issue with clocking or connections. 

 

Hope that helps get you going! 

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Observer
Observer
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Registered: ‎05-16-2014

I am currently trying to run a non-PIPE simulation of the DMA/Bridge Subsystem v4.0 endpoint core, with PL_SIM_FAST_LINK_TRAINING set to true. I am using the Root Port Model that was generated with the example design. I believe the link is in training as I see activity on both TX and RX after awhile. See screenshot. How long should I expect this to take in simulation? On the order of milliseconds? If I use PIPE mode sim, how much will that speedup link training? I generated the example design and endpoint core using Vivado 2018.3. Thanks

 

pcie link up.jpg

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