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hirschdaumen
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Registered: ‎04-13-2010

PL_FAST_TRAIN is not passed through to the PCIe core

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I'm doing a PCIe design with Vivado 2016.1 which is generally an upgrade from a Spartan-6 design to Artix-7.

 

In ISE I used the FAST_TRAIN generic to speed up the simulation time, and wanted to use the PL_FAST_TRAIN to do the same in Vivado. But I had to notice that there are no means to pass the PL_FAST_TRAIN to the core, because the pcie_7x_0 top-level wrapper file doesn't provide any generics.

 

So I looked at the example design, which in fact gets the PL_FAST_TRAIN passed from the testbench, but the only place the generic is used is in a constant declaration:

constant LNK_SPD : integer := get_gt_lnk_spd_cfg(PL_FAST_TRAIN);

And this constant is not used anywhere.

 

Is that supposed to be so?

How do I tell the PCIe core that it is in a simulation?

 

Regards

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hirschdaumen
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Registered: ‎04-13-2010

Answering myself..:

 

No generics are passed through to the core. There is even an note in PG054:

 

However, the parameters from the top-level file are not passed to the core_top.v/core_top.vhd module. Instead, the core top module is automatically assigned the parameters from the Vivado IDE. To check that the proper parameter values are being driven, refer to the core_top module.

 

In pcie_7x_0_core_top.vhd the PL_FAST_TRAIN is set as "TRUE" for the sub-modules, with the correct synthesis_off/on pragmas. So, the simulation is already "fast".

 

Don't know what the purpose of all the wrapper files is, but anyway, case closed.

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hirschdaumen
Adventurer
Adventurer
6,787 Views
Registered: ‎04-13-2010

Answering myself..:

 

No generics are passed through to the core. There is even an note in PG054:

 

However, the parameters from the top-level file are not passed to the core_top.v/core_top.vhd module. Instead, the core top module is automatically assigned the parameters from the Vivado IDE. To check that the proper parameter values are being driven, refer to the core_top module.

 

In pcie_7x_0_core_top.vhd the PL_FAST_TRAIN is set as "TRUE" for the sub-modules, with the correct synthesis_off/on pragmas. So, the simulation is already "fast".

 

Don't know what the purpose of all the wrapper files is, but anyway, case closed.

View solution in original post

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Registered: ‎07-22-2019
Hi Guy, You answer me one question about the same thing.
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