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veekshitha
Adventurer
Adventurer
424 Views
Registered: ‎08-13-2019

PL pcie and 100G Ethernet reference design

hi,

Where can I find reference design to implement PL pcie and 100G Ethernet integrated blocks in zynq ultra scale+ device.

Regards,

Veekshitha

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karnanl
Xilinx Employee
Xilinx Employee
353 Views
Registered: ‎03-30-2016

Hello @veekshitha 

I am not aware of any XAPP or TRD for the application you are looking for , but we do have Example Design that may helpful.

You can start with PG203 for 100GE Example Design
https://www.xilinx.com/support/documentation/ip_documentation/cmac_usplus/v3_0/pg203-cmac-usplus.pdf#page=111

You can start with PG213 for PCIe Example Design
https://www.xilinx.com/support/documentation/ip_documentation/pcie4_uscale_plus/v1_3/pg213-pcie4-ultrascale-plus.pdf#page=317


Regards
Leo


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