PLBV46 PCIe bridge access to DDR3 issue

[jmonteiro-dme]

Hi,

I'm using the PLVV46 PCIe bridge to exchange data between my PC and a uBlaze system. I'm able to access all the addressable space exept for the DDR3 (RAM) space. It allways returns 0xFFFFFFFF.

Can't the bridge directly access the RAM as it does for all other addressable space in the PLB?

Best,

JM

[jmonteiro-dme · Accepted solution]

I had to add a PLB access port to the DDR.

[changxiaolong]

       I am very glad to see that you know about pcie bridge, I am new to pcie and start to study it recent days. I have configed  my hard ware with macroblaze and use pcie as a peripheral equipment. i don't kown how to write a code to make it running . my question is do you have an example to show me how to write communication programs . thank you .

  my email is changxiaolon@163.com.

  wait for your answer,thank you very much

[jmonteiro-dme]

Hi Chang,

You should read this post i made some time ago:

http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/using-quot-PCI-Express-amp-DDR3-SDRAM-amp-User-design-circuit/m-p/84168#M3165

Regarding the SW it depends, what do you want to do exactly?

Best,

JM

[changxiaolong]

     Hi, Dear  jmonteiro-dme

              I appreciate that you answer my question. as a new people to pcie, I even don't kown how to propose my question exactly. but i want to introduce what I have done and what i want to do, hope that you can give me some advice.

             the style of my board is "xilinx xupv5-lx110t evaluation platform", i use xps to design a macroblaze core which include pcie_bridge IP core and use sdk to program.

             what i want to do is  to send and recive data from pc to my mcroblaze or from  mycroblze to pc through pcie interface.

             note that : the problem is that i don't how to program in sdk , how to make macroblaze  send or recive data from the  pcie interface.

            so, can you give me some example to show me how to program to realize the target in sdk.

[pureyou]

Hi，I have the same problem.But I don't know what is the meaning of "add a PLB access port to the DDR" .

Could you tell me the detail steps to configure the plb_pcie to map the BRAM or DDR? My board is ML605

[hgleamon1]

This thread is marked as solved so you should probably start a new thread if you have issues configuring the PCIe to DDR interface.

However, in short, you should do the following:

1. Add the Multiport Memory Controller IP.

2. Configure it to have at least 1 PLB interface. Also set which MCB you wish to use in your device.

3. Configure the MPMC for your type of memory.

4. Connect the MPMC to the PLB in the Bus Interfaces window of XPS.

5. Generate an address for the IP.

6. Configure the PCIe BAR to translate to the MPMC PLB address. I use a separate BAR dedicated to the memory.

Hope this helps.

Regards,

Howard

[qswsjs]

Thank you very much for your reply! can you attach your mhs file? I have problem config pcie on plb bus.thanks