08-15-2018 06:09 PM
Using Artix-7, 35T, CSG325 package device. After vibration tests we see failure in enumeration (PCIe, Gen2) with host. Our board is an endpoint and it was working all along until we subject the board to vibration tests.
While debug noticed "int_qplllock_out" bit and it indicated that PLL is not getting locked. Following are few additional points probed: -
1> Measured all the rails and they are within the limits, inclusive of MGTAVCC and MGTAVTT.
2> Had a doubt that solder balls disturbed due to vibration. To clarify, tapped the 100 MHz ref clock to IO pin and found okay. Converted the diff 100MHz clock (input from host) to single ended and fed to IO pin for this debug.
3> Ensured PCIe_Reset (from host) reaching the FPGA as this also verified by tapping to an I/O for this debug.
4> FPGA successfully gets self-configured (from ext SPI flash) within 84mS. This is well within the PCIe enumeration requirement that endpoint to be ready with 110mS.
5> For our internal logic, 62.5 MHz is successfully derived from the ref 100MHz clock.
6> Tested this faulty board in compliance base board (PCIe). For transmit compliance test, this board is not sending out expected transmit pattern. Used Xilinx provided IBERT bit file to transmit this pattern.
For Tx compliance the FPGA expects ref clock to be supplied and PCIe_Reset (from host) to be released. They both are done but still no transmit pattern coming out of FPGA with all the required voltage rails are healthy. Please note, we subjected two boards to vibration test and in which one board is exhibiting this fail behavior.
Now, as FPGA is working for self configuration (successfully loading from external flash) and with the above observations what could be the issue for PLL missing the lock? Any chance for specific section in FPGA (like PLL) damaged? Please provide your suggestions / comments...
Please note: This board was working fine for about 6 to 7 days of regressive tests. Also we conducted many EMI/EMC tests successfully. After vibration we see this fail behavior..
Thank you - Babu
08-16-2018 03:29 AM
What are you generating the clock from ?
if its a resonance / harmonic clock device, like a crystal or a tuning fork or resonator, its a mechanical thing,
These have limited vibration resistance, unless you select a mil grade device.
( they are actually micro-phonic , if you look with a phase domain analyser, you can see the output of them change if you shout at them. The other classic is the output frequency changes with vibration from fans )
PCIe pll have a very tight requirement on jitter, that a mechanical oscillator might not meet over vibration,
choose a better frequency source for your application
08-16-2018 10:04 AM
The clock is issued from host and it is well controlled in jitter. Because in the same PCIe slot when other card is plugged, no issue.
Also, when this faulty card is plugged to compliance base board which has better clock source, still PLL fails to lock..
Thanks - Babu
08-16-2018 12:44 PM
The qplllock indication might be a red herring, as the Artix 7 does not have QPLLs. I would open the implemented design in Vivado and see what is driving that signal.