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Visitor
Visitor
5,005 Views
Registered: ‎08-25-2009

Payload Transaction flow on PCIexpress devices

Hi,

 

I am working on PCIexpress Endpoint block plus devices v1.13.

 

Can anybody explain about flow of Payload transactions on the PCIexpress architecture?.

 

Regards,

Sekar.

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Xilinx Employee
Xilinx Employee
4,944 Views
Registered: ‎04-06-2010

What do you mean, "the flow of Payload transactions" ?

Can you please elaborate

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Visitor
Visitor
4,929 Views
Registered: ‎08-25-2009

Hi,

 

Thanks for your reply.

 

I am trying to access payload Data transaction greater than 1DW  with the xilinx User Application which is generared along with  PCIexpress endpoint block plus core (V1.13). But the user application is not supported for more than 1DW payload data (Memory Read Request).

 

In PCI express architecture, Requester (CPU or Root complex) will send the Memory Read request to endpoint and "Payload Data Length"  will be accomodated into Memory Read Request TLP.  Is my statement correct?.

 

I generated the PCIexpress end point  block plus core (V1.13) with 512 Bytes Max. Payload size. In this case, processor can request the payload data upto 512 bytes. Now My application  is sending Memory Read request for 1DW payload data and I could read the single 32 bit data for that Memory read request.  Burst data ( more than 1DW Payload Data transfer) read transfer is required for my application without need of Bus Master DMA method.

 

 

What is the procedure to send the Memory read Request  to end point device for no. payload data in b/w range of 1DW to 512 Bytes.  I think,  definetly It can only be achieved through software (application or driver).

 

Please guide me.

 

Regards,

Sekar. 

 

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