cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Anonymous
Not applicable
7,812 Views

Pcie reference design on Spartan SP605 board

Jump to solution

Hi all,

 

I'm trying to build the pcie reference design for the Spartan6 SP605 board.

 

If I choose VHDL in the coregen project the design doesn't work properly:  when I try it connected to a pcie slot in my PC the PC crashes when I try to read the memory with the pcitree program, and if I try the linux driver and example from xapp1022 it throws incorrect data when reading: always 0xFFFFFFFF.

 

But if I do the reference design choosing Verilog in coregen everything works OK.

 

I also have tried to do a mix project, some files in verilog and some in VHDL, to try to isolate the error. Finally I have found that the error is in the PIO_32_RX_ENGINE: I use a project with all generated files in VHDL except the PIO_32_RX_ENGINE that I use the verilog version, and it works OK.

 

Any clues about that? I don't know verilog enough to compare both versions and find the mistake.

 

Regards,

 

Pablo

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Newbie
Newbie
9,142 Views
Registered: ‎02-11-2010

Hi Pablo,

 

I had the same problem with the SP605 ref board when using VHDL as the top language. I found that the "req_compl_with_data_o" signal was not properly initialysed in the provided VHDL design. You should change the following two lines in the "PIO_32_RX_ENGINE.vhd" file :

 

req_compl_with_data_o    <= '1' after TCQ;     -- line 162, was '0' in the original file

req_compl_with_data_o    <= '1' after TCQ;     -- line 184, was '0' in the original file

 

Regards,

 

Simon

View solution in original post

5 Replies
Highlighted
Newbie
Newbie
9,143 Views
Registered: ‎02-11-2010

Hi Pablo,

 

I had the same problem with the SP605 ref board when using VHDL as the top language. I found that the "req_compl_with_data_o" signal was not properly initialysed in the provided VHDL design. You should change the following two lines in the "PIO_32_RX_ENGINE.vhd" file :

 

req_compl_with_data_o    <= '1' after TCQ;     -- line 162, was '0' in the original file

req_compl_with_data_o    <= '1' after TCQ;     -- line 184, was '0' in the original file

 

Regards,

 

Simon

View solution in original post

Highlighted
Anonymous
Not applicable
7,782 Views

Thank you very much!

 

It works OK now.

 

Can't understand how Xilinx tools may have this kind of silly bugs . . .  

 

Regards,

 

Pablo

0 Kudos
Highlighted
Visitor
Visitor
7,549 Views
Registered: ‎03-03-2010

thanks,

 

 

this post also helped me !!!! :)

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
7,487 Views
Registered: ‎09-02-2009

Hi all,

 

Sorry for any problems this has caused.  This issue will be fixed when 12.1 is released.

 

Jason

0 Kudos
Highlighted
Newbie
Newbie
6,958 Views
Registered: ‎05-19-2010

I have another problem that apparently you did not have, it is the UCF file. It seems that the UCF file delivered online is not the good not. Would it be possible that you send me (of display in this forum) the UCF that you used for the Pcie reference design ?

 

Thanks

0 Kudos