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Voyager
Voyager
591 Views
Registered: ‎10-31-2016

Pcie send and recieve data simultaneously (Artix 7)

Hello, 

 

when I see 7 series integrated PCIe Ip core example, it seems that that Pcie read data from the PC regarding the tlp example address, tag, etc. then send the tlp on s_tx. this implies both m_rx and s_tx is busy during sending data to PC from FPGA. Is it possible to free m_rx, so that I can send data on s_tx and receive data on m_rx simultaneously?

 

Best regards 

 

Thanks 

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1 Reply
Xilinx Employee
Xilinx Employee
500 Views
Registered: ‎08-02-2007

Re: Pcie send and recieve data simultaneously (Artix 7)

from PCIE IP's pespective the tx and rx can work simultaneously

in the example is

1 Root start to write the EP's 10 address

2 Root read it back

 

 

 

 

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