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eric_fpga
Observer
Observer
11,024 Views
Registered: ‎09-01-2014

Problem about "PCI_LC_I" file in 32bit target/initiator PCI Core

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Hi 

I've got an evaluation license for PCI Core,when I using the "ping" example,there is a file named "PCI_LC_I".On the top of this file there is a comment says "This file cannot be synthesized and should only be used
with supported simulation tools".So how can I get a proper file for synthesizing?

Can someone help me?

thanks

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kotir
Scholar
Scholar
19,059 Views
Registered: ‎02-03-2010

Hi,

 

PCI_LC_I.v/vhd is the structual simulation netlist file. This is not for synthesis.

You can add this but will not be synthesized as the simulation part of the file is seperated by synopsys_translate off attribute.

It will not cause error even if you add this to synthesis files.

 

If you are using core gen then you might be using the v3.167.

For synthesis below are the files.

The netlist ngo file need to be pickedup from the src/xpci folder

 

ngo.png

 

Regards,

KR

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6 Replies
kotir
Scholar
Scholar
11,013 Views
Registered: ‎02-03-2010

Hi,

 

What exactly the device targetted and tool version ?

 

Regards,

KR

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kotir
Scholar
Scholar
11,005 Views
Registered: ‎02-03-2010

 

Hi ,

 

When i load an example design of PCI core targetted for A7. I see as below.

 

Green box points to files for synthesis and blue box points to simulation.

 

pci.png

 

Regards,

KR

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eric_fpga
Observer
Observer
11,002 Views
Registered: ‎09-01-2014

I'm using ISE 14.7 and i'm targeting SPARTAN3AN XC3S200AN-5ftg256

what shoud I do with this tools and this target?

thanks

 

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yenigal
Xilinx Employee
Xilinx Employee
10,978 Views
Registered: ‎02-06-2013

Hi

 

 

You need to use the netlist file instead of the simulation file.

 

Check below AR

 

http://www.xilinx.com/support/answers/10235.html

Regards,

Satish

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kotir
Scholar
Scholar
19,060 Views
Registered: ‎02-03-2010

Hi,

 

PCI_LC_I.v/vhd is the structual simulation netlist file. This is not for synthesis.

You can add this but will not be synthesized as the simulation part of the file is seperated by synopsys_translate off attribute.

It will not cause error even if you add this to synthesis files.

 

If you are using core gen then you might be using the v3.167.

For synthesis below are the files.

The netlist ngo file need to be pickedup from the src/xpci folder

 

ngo.png

 

Regards,

KR

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

View solution in original post

eric_fpga
Observer
Observer
10,972 Views
Registered: ‎09-01-2014

Thank you very very much,it works.

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