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Contributor
Contributor
813 Views
Registered: ‎10-15-2018

Problem in performing DMA data transfer using MSI interrupt in XDMA-MM example design

Hi,

I am new to PCIe and would like to seek help in performing DMA transfer using MSI interrupt in XDMA-MM example design.

I am trying to perform DMA transfer between Virtex-7 Series FPGA board (VC707) and host PC Windows 10 through PCIe, and I want to perform the DMA transfer using MSI interrupt. The software driver that I'm using is the example XDMA software driver from Jungo Connectivity.

Using DMA/Bridge Subsystem for PCI Express v4.1 IP core, I have implemented 2 user interrupts. Then I generated its AXI4-MM Example design with User IRQ Example Design attached to it (pg 100 of pg195-pcie-dma).

Following shows the active address space:

1. Bar 0 (user IRQ registers) - (0x100000 bytes)

2. Bar 1 (PCIe to DMA registers) - (0x10000 bytes)

To allow MSI interrupt to take place, I disabled legacy interrupt by implementing interrupt disable in the PCI command register (write x0507 to the PCI command register (offset: x04 of PCI configuration registers)). Next I made sure that msi enable bit is set to '1' in the MSI control register (offset: x49 of PCI configuration registers) [Data reads x00 81 in MSI control register].

After which, I accessed to Bar 1 (PCIe to DMA registers space) to enable the user interrupt. Following are the actions that take place in the PCIe to DMA registers space:

- set bit 0 to user interrupt enable mask (offset: x2004)

- set bit 0 to engine interrupt enable mask (offset: x2010)

- set (0x00001f1f) to IRQ Block User Vector Number (offset: x2080) to map IRQ usr_irq_req[1] to vector 1 and  usr_irq_req[0] to vector 0.

-set (0x1f00001f) to IRQ Block Channel Vector Number (offset: x20A0) to map channel 0 to vector 0 for c2h channel and h2c channel.

Finally, I asserted usr_irq_req by setting bit 1 to the interrupt control register (register offset: 0x08) at Bar 0 (user irq register space).

Using ILA to probe into the MSI enable register and the usr_irq_req register, I managed to see both MSI enable register and usr_irq_req register asserted (bit 1). The interrupt status register (register offset 0x0c read from Bar 0 user irq register space) reads 0x02.

With that, I tried to perform DMA transfer (from device to host) using interrupt method from the software driver. When I tried to do that, the PC either hang or reboot with an error (928-fatal pcie error; completion timeout).

Is there any step that I'm doing wrong, and how can I prevent the error from taking place?

Thanks

 

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4 Replies
Moderator
Moderator
713 Views
Registered: ‎02-16-2010

Re: Problem in performing DMA data transfer using MSI interrupt in XDMA-MM example design

@aliciachee

Whether "Bus Master enable" bit is set to 1'b1 in the PCIe configuration space?

Are you monitoring usr_irq_ack? When you receive a pulse on usr_irq_ack, you need to release usr_irq_req. Please check the timing diagram of MSI interrupts in figure 2-2 of PG195.

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Contributor
Contributor
698 Views
Registered: ‎10-15-2018

Re: Problem in performing DMA data transfer using MSI interrupt in XDMA-MM example design

Hi venkata,

 

Forgot to mention in the earlier post, I have also set the "Bus Master enable" bit  to 1'b1 in the PCIe configuration space.

I am monitoring usr_irq_ack. When I set "usr_irq_req" bit to 1'b1 and feed into the xdma pcie ip core, I did not manage to receive any pulse on usr_irq_ack. Anyone knows how to settle this situation? If not, is there anyone who has a workable XDMA design with MSI interrupt that can pass it to me?

Thanks

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Moderator
Moderator
685 Views
Registered: ‎02-16-2010

Re: Problem in performing DMA data transfer using MSI interrupt in XDMA-MM example design

@aliciachee

I believe the step below seems incorrect. 

set (0x00001f1f) to IRQ Block User Vector Number (offset: x2080) to map IRQ usr_irq_req[1] to vector 1 and  usr_irq_req[0] to vector 0.

 

To map IRQ usr_irq_req[1] to vector 1 and  usr_irq_req[0] to vector 0, bits [12:8] should be 5'h1 and bits [4:0] should be 5'h0. So you should be writing 0x00000020

After you write the above value and usr_irq_req is asserted, please read the following registers.

IRQ Block User Interrupt Request (0x40) -- offset 0x2040

IRQ Block User Interrupt Pending (0x48) -- offset 0x2048

 

Regarding the step below, I believe you are writing 1'b1 to bit0. Please confirm. If you are using usr_irq_req[1], you should write 1'b1 to bit1 of this register.

- set bit 0 to user interrupt enable mask (offset: x2004)

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Contributor
Contributor
634 Views
Registered: ‎10-15-2018

Re: Problem in performing DMA data transfer using MSI interrupt in XDMA-MM example design

Hi @venkata,

I managed to get usr_irq_ack asserted by following your step.

However, when I checked the h2c_status port, it stays at 0x60 status: IRQ event pending bit is high. In addition, when I tried performing DMA transfer using MSI interrupt from the device to Windows 10 host pc, I still continue to face an interrupt timeout error.

Any idea how can I move on from this?

Thanks!

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