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Visitor
Visitor
10,371 Views
Registered: ‎05-14-2012

Problem with B_GTXE2_CHANNEL when trying to simulate PCIe Core in ModelSim

Hi,

 

I'm trying to simulate the PCIe core in a Kintex-7 with Modelsim.

 

I've tried ISE13.4 & 14.1

 

I've generated the libraries with CompXLib...

 

When I start the simulation in modelsim, I get this error when it pass by PCIe_2X8_gt_wrapper

 

# Loading work.PCIe_2X8_gt_wrapper # Loading C:/Xilinx/14.1/ISE_DS/ISE/verilog/mti_de/10.1a/nt/unisims_ver.GTXE2_CHANNEL # ** Error: (vsim-3033) C:/Xilinx/14.1/ISE_DS/ISE/verilog/src/unisims/GTXE2_CHANNEL.v(3191): Instantiation of 'B_GTXE2_CHANNEL' failed. The design unit was not found. # #         Region: /board/EP/PCIe_2X8_i/gt_top_i/pipe_wrapper_i/pipe_lane[0]/gt_wrapper_i/gtx_channel/gtxe2_channel_i #         Searched libraries: #             C:\Xilinx\14.1\ISE_DS\ISE\verilog\mti_de\10.1a\nt\unisims_ver #             C:\Xilinx\14.1\ISE_DS\ISE\verilog\mti_de\10.1a\nt\unisims_ver

 

the simulator doesn't find 'B_GTXE2_CHANNEL'  in any libraries... neither I...

 

Can anyone help me with that?

 

Thanks

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4 Replies
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Visitor
Visitor
10,352 Views
Registered: ‎05-29-2012

Hi,

 

I've the same problem just with differnet interfece. I'm trying to simulate JEDEC204B (v2.1) generated by Xilinx Core Generator version 14.1.

 

    B_GTXE2_CHANNEL_INST (
                       |
ncelab: *E,CUVMUR (/cadappl/ictools/xilinx_ise/14.1/ISE_DS/ISE/verilog/src/unisims/GTXE2_CHANNEL.v,2959|23): instance 'demo_tb.DUT@jesd204_v2_1_example_design<module>.i_jesd204_v2_1_block@jesd204_v2_1_block<module>.i_gtwizard_v2_1_top@jesd204_v2_1_gtwizard_v2_1_top<module>.gtwizard_v2_1_i@jesd204_v2_1_gtwizard_v2_1<module>.gt0_gtwizard_v2_1_i@jesd204_v2_1_gtwizard_v2_1_GT<module>.gtxe2_i@GTXE2_CHANNEL<module>.B_GTXE2_CHANNEL_INST' of design unit 'B_GTXE2_CHANNEL' is unresolved in 'worklib.GTXE2_CHANNEL:module'.


Did you or anyone else found some solution of that?

 

Thanks

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Xilinx Employee
Xilinx Employee
10,324 Views
Registered: ‎04-06-2010

Within your vsim command do you make sure to include the following:

 

-L secureip

 

Let me know if you have already done that.

 

 

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Visitor
Visitor
10,305 Views
Registered: ‎05-29-2012

Hi luisb,
do you know if there is necessery some special license feature to compile the encrypted secureIP libraries for NC-VERILOG tool?
Because when I added then into the command line I obtained other error message:

ncverilog(64): 09.20-s038: (c) Copyright 1995-2011 Cadence Design Systems, Inc.
file: /proj/ibeta/users/ludekf/.caddata/xilinx/ISE_DS/ISE/secureip/ncsim/gtxe2_common_ncsim/gtxe2_common_001.vp
l=Q>[\@KNI999999T1r/v6bQbKRxxxijvtLch5VP3jPP58cezcFKU4wp2VrZ/AaoZffZg+EvFLCi
|
ncvlog: *F,DECERR (/proj/ibeta/users/ludekf/.caddata/xilinx/ISE_DS/ISE/secureip/ncsim/gtxe2_common_ncsim/gtxe2_common_001.vp,11|15): Error while decrypting : NO ERROR - Failed
unable to checkout license for encryption/decryption. 'lic_error -18'

My tool version is: ncverilog 09.20-s038

Thanks in advence!
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Visitor
Visitor
10,295 Views
Registered: ‎05-29-2012

Problem resolved...  newer version of the tool (ncverilog: 11.10-s022) doesn't need any special license feature.

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