cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
christophe0
Newbie
Newbie
4,461 Views
Registered: ‎06-17-2011

Problem with PCI Express Example on Spartan6

Hi,

 

I begin to  work with PCI Express and I want to run the example created by the Core Generator : the "PIO example design"

I have a Spartan6 (SP605).  

I create a empty project under ISE (12.4) and add a "Spartan-6 Integrated Block for PCI Express v.1.4" with the Core Generator (I don't modify any parameter).

Then I open the project "PCIe_EP_vhdl_example_project.xise" that has been created. This project contains the PCIe_EndPoint IP,  the PIO application and the constraint file. I create the bitstream file.

 

First Remark, If I add a "Spartan-6 Integrated Block for PCI Express v.2.2" instead, I can't pass the "Translate" step. I don't understand why (ERROR:NgdBuild:604 - logical block 'PCIe_EP_i/axi_basic_top_inst' with type   'axi_basic_top' could not be resolved).

 

For the 1.4 version, no problem to create the bitstream. I flash it with Impact, connect the SP605 on the motherboard of another PC. Then I start the PC (with Windows) and use PCITree, but I never see my endpoint to appear.

 

Where am I wrong?

 

Thank you for your help

0 Kudos
3 Replies
christophe0
Newbie
Newbie
4,459 Views
Registered: ‎06-17-2011

I forgot : the SP605 obtains its power from the DC power supply (J18)

0 Kudos
luisb
Xilinx Employee
Xilinx Employee
4,441 Views
Registered: ‎04-06-2010

If you want to get the PIO example design working on the SP605, I recommend running through xtp065.  You can find it here:

http://www.xilinx.com/products/boards/sp605/reference_designs.htm

 

Hope this helps.

0 Kudos
christophe0
Newbie
Newbie
4,436 Views
Registered: ‎06-17-2011

Thank you for your answer. I will try this (I did not know this documentation).

0 Kudos