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Adventurer
Adventurer
10,739 Views
Registered: ‎11-17-2009

Problem with blockplus pci express endpoint core in Xilinx ISE 13.4

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Hi,

I am working on a project that involve PCIe endblock, So i generated a BlockPlus PCI express endpoint core v 1.15 for virtex-5 device with coregen using Xilinx ISE 13.4. When i instantiate the core, I am getting a strange error. It says

ERROR:HDLCompilers:26 - "ipcore_dir/endpoint_blk_plus_v1_5/simulation/dsport/pci_exp_expect_tasks.v" line 6 expecting 'EOF', found 'reg'

 

I have checked for the closure of each ifdef and ifndef in every file and every one of them have corresponding to them. I have searched this forum and seen another source of error that you can not use multidimentional arrays and I have checked that this desing is not using any, only single dimension vectors o-bit signals are used, like

reg [31:0] error_file_ptr; or reg abc[31:0]

 

I have even checked replacing the above (first) statement with reg error_file_ptr[31:0] and adding some logic by my self, but there is no success.

 

I have attached the log file and the whole project.

 

Any help would be highly appreciated.

 

Best Regards,

Uzair

 

 

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Adventurer
Adventurer
15,248 Views
Registered: ‎11-17-2009

Removing xco file from the project and manually including the generated hdl files solves the problem. Using xco file is not the recommended way of using PCIe core as confirmed by the xilinx support.

 

Best Regards,

Uzair

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8 Replies
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Professor
Professor
10,737 Views
Registered: ‎08-14-2007

I just want to make clear that you are trying to simulate the design when this happens?  The file

in the error message is part of the simulation model, so it shouldn't show up during synthesis.

Another possibility is that there is a problem parsing the model for the hard PCIe endpoint block,

which is delivered encrypted.  Still, it seems you were on the right track looking at `ifdefs because

the error is no doubt in the file processed before the one in the error message.

 

-- Gabor

-- Gabor
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Adventurer
Adventurer
10,735 Views
Registered: ‎11-17-2009

Thanks for your quick reply. I am not simulating the design and actually implementing it on hardware as i have used some much earlier version of this core.

Can you give me some advice or suggestion.

 

Thanks and Best Regards,

Uzair

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Xilinx Employee
Xilinx Employee
10,724 Views
Registered: ‎06-01-2011

Hi Uzair,

 

I had skim over your project. First thing, you should change your `ifdef slightly. I see that you commented the first task of the ifdef and that you left with the ifdef in the "else" condition. If this is what you wanted, you should just remove the `ifdef completely and just execute that "task" (or "parameter" in your situation).

Two reasons for this. First, It's probably complaining because the if statement hasn't ended before it sees the else statement and that can cause it to not close the function properly.

And second, what if the if-statement is "false", in which case you'll not be passing down that parameter at all when instantiating which may cause unforseen issues.

 

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Adventurer
Adventurer
10,720 Views
Registered: ‎11-17-2009

Hi ckarman,

 

Thanks for your response.

I haven't change even a single line in this core. I have just instantiated it. The thing you are mentioning is done in many files. can you please tell me which file you are talking about?

 

Best Regards,

Uzair

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Professor
Professor
10,713 Views
Registered: ‎08-14-2007

This is what bothers me:

 

ERROR:HDLCompilers:26 - "ipcore_dir/endpoint_blk_plus_v1_5/simulation/dspo

rt/pci_exp_expect_tasks.v" line 6 expecting 'EOF', found 'reg'

 

You should make sure you are instantiating the correct files for synthesis.  This looks like you have

instantiated the simulation model instead.

 

-- Gabor

-- Gabor
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Adventurer
Adventurer
10,711 Views
Registered: ‎11-17-2009

Hi Gabor,

Thanks for your quick reply.

I am not doing the simulation, i have just use the HDL instantiation template generated by the ISE (also attached with this message). This instantiation template can be generated by the view HDL instantiation template option in the ISE. There is a `ifdef on 'SIMULATION' that i suppose enables the simulation. I have double checked this that this parameter is not defined in the project.

 

Best Regards,

Uzair

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Xilinx Employee
Xilinx Employee
10,706 Views
Registered: ‎06-01-2011

Hi Uzair,

 

Maybe I was looking it wrong. I just opened your ISE project (PCIeCoreTest) and there's only one HDL file (ipb_oregon_nic_xilinx_v5) that instantiates the PCIe core.

In this HDL, I saw these:

       `ifdef SIMULATION       

       // .fast_train_simulation_only(1'b1),       

       `else       

      .fast_train_simulation_only(1'b0),       

      `endif

 

       `ifdef TWO_PLM_AUTO_CONFIG       

       // .two_plm_auto_config(2'b11),       

       `else       

       .two_plm_auto_config(2'b00),       

       `endif

 

I was thinking, maybe you can just remove the ifdef and pass on the parameters directly since you're not doing sim anyway.

 

I also saw that you instantiating the .xco. Like Gabor said, it somehow tried to instantiate the RP simulation model (dsport). You may try, removing your XCO from your project and import all the sources in the ipcore_dir/<ip name>/source. If you do it this way and didn't include any sources from the /simulation/dsport folder, we hope that it won't try to pull in the simulation model anymore.

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Adventurer
Adventurer
15,249 Views
Registered: ‎11-17-2009

Removing xco file from the project and manually including the generated hdl files solves the problem. Using xco file is not the recommended way of using PCIe core as confirmed by the xilinx support.

 

Best Regards,

Uzair

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