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Observer
Observer
9,687 Views
Registered: ‎12-28-2013

Problem with interrupt, V7 PCIe Gen3 endpoint

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Hi,

 

I'm working on a project involving Virtex-7 Gen3 Integrated Block for PCI Express v1.7 (endpoint). I need to transfer data from V7 to CPU memory by DMA.


At first I choose legacy interrupt, in simulation the rootport received Mwr TLPs successfully, but couldn't receive legacy interrupt. The signal cfg_interrupt_sent had been asserted twice by the core (Assert INTA and Deassert INTA), the interrupt disable bit in the PCI command register was left 0 as default, and the attribute AXISTEN_IF_ENABLE_MSG_ROUTE was set to 18'h2FFFF.  Then I tried the PIO example design simulation, and no legacy interrupt was received either.


Later, I used MSI interrupt mode, but cfg_interrupt_msi_enable wouldn't be asserted with this command:
board.RP.tx_usrapp.TSK_TX_TYPE0_CONFIGURATION_WRITE (board.RP.tx_usrapp.DEFAULT_TAG, 12'h48, 32'h00010000, 4'b0100);

 

I'm now very confused. Could anyone give me some help?

Thanks ahead.

 

David

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Scholar
Scholar
15,413 Views
Registered: ‎02-03-2010

Re: Problem with interrupt, V7 PCIe Gen3 endpoint

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can you make sure you are able to set AXISTEN_IF_ENABLE_MSG_ROUTE in the file pcie3_7x_0_pcie_7vx. Not in the xilinx_pcie_3_0_7vx_rp.v. This value is not passed to the underlying hierarchy.

 

I did this and able to see the packet on CQ interface.

 

I just added the below code which writes to CCCCDDDD to address EEC address in Bar0.

 

Below is the pkt i see at rp's CQ interface.

 

CQ.png

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Scholar
Scholar
15,414 Views
Registered: ‎02-03-2010

Re: Problem with interrupt, V7 PCIe Gen3 endpoint

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can you make sure you are able to set AXISTEN_IF_ENABLE_MSG_ROUTE in the file pcie3_7x_0_pcie_7vx. Not in the xilinx_pcie_3_0_7vx_rp.v. This value is not passed to the underlying hierarchy.

 

I did this and able to see the packet on CQ interface.

 

I just added the below code which writes to CCCCDDDD to address EEC address in Bar0.

 

Below is the pkt i see at rp's CQ interface.

 

CQ.png

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Give Kudos to a post which you think is helpful.
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View solution in original post

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Observer
Observer
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Registered: ‎12-28-2013

Re: Problem with interrupt, V7 PCIe Gen3 endpoint

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hi, kotir

 

Thank you for your reply.

 

Thanks to your reply, I note that the attribute AXISTEN_IF_ENABLE_MSG_ROUTE set in rp.v is not passed to the underlying hierarchy. Thus, I set this attribure to 18'h2FFFF in pcie3_7x_v1_7_pcie_3_0_7vx.v which I see is the topest module uses it in the PIO example design.

 

I write CCCCDDDD to address board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0] + 11'h6ec in bar0.

I can see that both the signals gen_leg_intr and cfg_interrupt_sent are asserted

 

But the rootport still doesn't receive any packet.

 

Looking forward to your further advice. Thank you .

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Scholar
Scholar
9,582 Views
Registered: ‎02-03-2010

Re: Problem with interrupt, V7 PCIe Gen3 endpoint

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Hi ,

 

Can you use the below code as is,

 

                          board.RP.tx_usrapp.DATA_STORE[0] = 8'hDD;
                          board.RP.tx_usrapp.DATA_STORE[1] = 8'hDD;
                          board.RP.tx_usrapp.DATA_STORE[2] = 8'hCC;
                          board.RP.tx_usrapp.DATA_STORE[3] = 8'hCC;

                          board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_32(board.RP.tx_usrapp.DEFAULT_TAG,
                              board.RP.tx_usrapp.DEFAULT_TC, 11'd1,
                              board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+11'hEEC, 4'h0, 4'hF, 1'b0);

 

 

Make sure you set the Bus master enable bit on both RP and End point.

 

Regards,

KR

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Observer
Observer
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Registered: ‎12-28-2013

Re: Problem with interrupt, V7 PCIe Gen3 endpoint

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With your help I solve the problem,  please accept my late thanks.

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