01-13-2013 05:38 AM
I'm new to FPGA design, and have the lofty goal of developing a PCIe device. I am somewhat familiar with the PCIe spec. I've begun with some basic tutorials, and have tried out the example design with the PCIe core for the SP605 dev board, but I've had trouble getting the DMA example (XAPP 1502) to work as expected. I have successfully built the example design for the Spartan Integrated Block for PCI Express, and downloaded the bitstream to the SPI flash. When connected to a PCIe bus the device is discovered and appears in `lspci` output on Linux, and the LED indicating that the link is up is lit. This works fine for both v1.4 and 2.4.
I have successfully built XAPP 1502 as per the instructions using v1.4 of the Spartan Integrated Block for PCI Express (a number of errors are generated when building with v2.4); however, when the bitstream is downloaded to the device and the board is connected to a PCIe bus, no status LEDs are lit and the device does not appear in the `lspci` output.
I realise this is sounding like a "it doesn't work" question, but there's a lot of documentation to wade through which is pretty daunting for a newcomer, so I'm hoping someone can point me in the right direction to get started debugging this.
01-22-2013 02:14 AM
01-23-2013 04:13 PM
I think it's resolved, the bitstream seems to work properly.
I was able to build the example design for the PCIe core successfully, but the DMA performance demo code (using the implement_dma.pl) script did not work properly as described. I took the xst.prj file (project/bmd_design/implement/xst.prj) from the example design, and replaced it with the list of files used for the SP605 in the DMA demo:
verilog work "../source/bmd_design.v"
verilog work "../source/pcie_bram_top_s6.v"
verilog work "../source/pcie_brams_s6.v"
verilog work "../source/pcie_bram_s6.v"
verilog work "../source/gtpa1_dual_wrapper_tile.v"
verilog work "../source/gtpa1_dual_wrapper.v"
verilog work "../example_design/xilinx_pcie_1_1_ep_s6.v"
verilog work "../dma_performance_demo/fpga/BMD/s6_pci_exp_32b_app.v"
verilog work "../dma_performance_demo/fpga/BMD/BMD_32_RX_ENGINE.v"
verilog work "../dma_performance_demo/fpga/BMD/BMD_32_TX_ENGINE.v"
verilog work "../dma_performance_demo/fpga/BMD/common/BMD.v"
verilog work "../dma_performance_demo/fpga/BMD/common/BMD_CFG_CTRL.v"
verilog work "../dma_performance_demo/fpga/BMD/common/BMD_EP.v"
verilog work "../dma_performance_demo/fpga/BMD/common/BMD_EP_MEM.v"
verilog work "../dma_performance_demo/fpga/BMD/common/BMD_EP_MEM_ACCESS.v"
verilog work "../dma_performance_demo/fpga/BMD/common/BMD_INTR_CTRL.v"
verilog work "../dma_performance_demo/fpga/BMD/common/BMD_INTR_CTRL_DELAY.v"
verilog work "../dma_performance_demo/fpga/BMD/common/BMD_RD_THROTTLE.v"
verilog work "../dma_performance_demo/fpga/BMD/common/BMD_TO_CTRL.v"
Then I could build using the implement.sh in the same implement directory. I modified the design slightly so that the bus mastering is enabled by default and that seemed to have changed when I downloaded the new bitstream to the device. I am very new to FPGA development and the ISE suite (but have a software dev background), so please excuse my "uh I did this and it seems to have changed" approach to verifying :)