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Visitor justry
Visitor
15,367 Views
Registered: ‎06-20-2013

Problems of PCIE DMA simulation

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hi, all,

         Recently i met a problem of pcie dma read data from system memory.

         I've created a PCIe EP core for the virtex 5 lx110t. I tried to run the example simulation. I code the DMA controller myself. And the Root Complex can read/write bar0 in the EP.

         But the RX of the Root complex could not receive read request from EP when the DMA_TX module of the DMA controller send a read request to Root complex. 

        WP_20130621_002.jpg

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WP_20130621_003.jpg

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I've attached here with the log message of my simulation. 

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WP_20130621_005.JPG

 

          i can't unsterdand why the root complex recognize the read request as unsupported request. And what is the problem that cause this situation?

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1 Solution

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Scholar kotir
Scholar
24,127 Views
Registered: ‎02-03-2010

Re: Problems of PCIE DMA simulation

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This error message is reported if the 'Memory Address Decoder Enable' bit of the command register of the Root Port Configuration Space is not set. This can be checked by looking at the cfg_command[1] signal in simulation.

 

The required tasks are already in the test bench of root port. You just need to call them  in your test bench. The tasks are the file pci_exp_usrapp_tx.v.
 
    //--------------------------------------------------------------------------
    // Direct Root Port to allow upstream traffic by enabling Mem, I/O and
    // BusMstr in the command register
    //--------------------------------------------------------------------------
 
    board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);
    board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000001, 32'h00000007, 4'b1110);
    board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);

 

 

i hope the above suggetion helps.

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10 Replies
Visitor justry
Visitor
15,366 Views
Registered: ‎06-20-2013

Re: Problems of PCIE DMA simulation

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sorry for my poor English and the rough pictures.

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Scholar kotir
Scholar
24,128 Views
Registered: ‎02-03-2010

Re: Problems of PCIE DMA simulation

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This error message is reported if the 'Memory Address Decoder Enable' bit of the command register of the Root Port Configuration Space is not set. This can be checked by looking at the cfg_command[1] signal in simulation.

 

The required tasks are already in the test bench of root port. You just need to call them  in your test bench. The tasks are the file pci_exp_usrapp_tx.v.
 
    //--------------------------------------------------------------------------
    // Direct Root Port to allow upstream traffic by enabling Mem, I/O and
    // BusMstr in the command register
    //--------------------------------------------------------------------------
 
    board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);
    board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000001, 32'h00000007, 4'b1110);
    board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);

 

 

i hope the above suggetion helps.

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
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Visitor justry
Visitor
15,285 Views
Registered: ‎06-20-2013

Re: Problems of PCIE DMA simulation

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thanks for your suggestion. I resolved the problem by setting the "bus master bit" 1 which is default zero.

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Visitor by991
Visitor
14,897 Views
Registered: ‎12-23-2013

Re: Problems of PCIE DMA simulation

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which parameter is bus master bit?

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Xilinx Employee
Xilinx Employee
14,894 Views
Registered: ‎08-02-2007

Re: Problems of PCIE DMA simulation

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Bit 2 of command register

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Visitor by991
Visitor
14,875 Views
Registered: ‎12-23-2013

Re: Problems of PCIE DMA simulation

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i want to simulate CPLD TLP, i configured the command register bit 2 to 1'b1, then sent the TSK_TX_COMPLETION_DATA, but the EP could not receive the CPLD TLP, what's the problem?

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Visitor guuch
Visitor
14,543 Views
Registered: ‎03-31-2014

Re: Problems of PCIE DMA simulation

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I meet the same problem with you,how do you solve the problem that sent the TSK_TX_COMPLETION_DATA, but the EP could not receive the CPLD TLP.


@by991 wrote:

i want to simulate CPLD TLP, i configured the command register bit 2 to 1'b1, then sent the TSK_TX_COMPLETION_DATA, but the EP could not receive the CPLD TLP, what's the problem?


 

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Observer zhangziyi
Observer
3,202 Views
Registered: ‎10-12-2017

Re: Problems of PCIE DMA simulation

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please tell us how to solute the problem,,,,,thanks
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Observer zhangziyi
Observer
3,189 Views
Registered: ‎10-12-2017

Re: Problems of PCIE DMA simulation

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RP sent the TSK_TX_COMPLETION_DATA, but the EP could not receive the CPLD TLP. Where wroung?
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Observer nagakiranjapan
Observer
1,312 Views
Registered: ‎05-17-2018

Re: Problems of PCIE DMA simulation

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HI Zhang,

 

Check for Max payload size parameter configured for RP as well as EP.

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