Unfortunately I have only tried this on Linux.
I tried to make the cpp source driver and sip as platform independent as possible but I don't have much experience with coding for Windows. I used the example userland drivers provided by Xilinx to write the library but after looking at my two Makefiles, they don't seem to be compatible with Windows.
It seems as though the right path to get this running on Windows is probably the following:
1. Modify the 'Makefile' in the base directory to build a library for Windows. (Err, just tried this... where is 'make' in windows?)
2. Install SIP for Windows and run the 'configure.py' in the sip directory, this should generate a windows friendly 'Makefile'
3. Make and install the sip module generated.
4. Figure out how to tell the python module where the AXI Lite Interface is on Windows, as an example on my Linux system the AXI Lite Interface is located "/dev/xdma/card0/user".
5. Modify the device_map.json file with your addresses of the core.
6. Run the 'demo_block_ram_driver.py' with the flag --driver "Address\of\axi lite pcie"
I tried to write the python to be 2/3 agnostic but there might be some issues with Python3. There isn't much code so it shouldn't be too hard to fix any issues.
I wish you luck
Dave
