Hi Xilinx-ers,
Describing in PG302, AXI4-Stream C2H Completion interface is used to transfer "completion data" such as the length of the packet transferred in bytes, error, color bit and user data. PG302 also mentions that "every completion packet has a corresponding C2H data packet".
I wonder about the timing relation between "AXI4-Stream C2H" and "AXI4-Stream C2H Completion". PG302 does not provide enough information for that issue.
Anyone can help?
There is the following mention in the product guide. Are you looking for any specific information? Also, please provide use-case scenario.
Thanks.