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dsakjl
Explorer
Explorer
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Registered: ‎07-20-2018

QDMA: H2C TUSER ERROR

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Hello everyone,

We are using QDMA IP version 3 with patch AR73179 on Vivado 2019.2, and Xilinx
driver (https://github.com/Xilinx/dma_ip_drivers/tree/master/QDMA/linux-kernel).

In AXI4-Stream H2C Ports list there is the port m_axis_h2c_tuser_err which,
as stated by the documentation, "If set, indicates the packet has an error.
The error could be coming from PCIe, or QDMA might have encountered a double
bit error." (PG302, p.96).

In case of a multiple beats packet, is this signal asserted for all the beats
or just for a subset of them?

Please, can you help us on this?

Thank you.

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deepeshm
Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2008

Hi, How often or rarely it will get triggered depends on how error prone the system is. It will be active since the first beat that saw the error and will be asserted till the end of the packet. User is recommended to look at error registers and context for details on the reason behind the triggering of the signal. Let me know if you need further details.

Thanks.

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dsakjl
Explorer
Explorer
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Registered: ‎07-20-2018

Hello everyone,

the QDMA 3.0 IP documentation reports that:

"The regular C2H data packet can be multiple beats."

(page 47, https://www.xilinx.com/support/documentation/ip_documentation/qdma/v3_0/pg302-qdma.pdf)

From that definition it seems that the documentation refers to packets as something which could be formed by one or more beats.

So the interface signal m_axis_h2c_tuser_err, which "If set, indicates the packet has an error." should be consistent across all the packet's beats.

Please, can you confirm or deny that?

Thank you, best regards.

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deepeshm
Xilinx Employee
Xilinx Employee
404 Views
Registered: ‎08-06-2008

The error signal is a generic indication of error in the traffic data. The error source should be investigated by checking various registers and lspci log to identify the source of the issue. We will update the document in a future release to reflect this explanation. 

Thanks.

dsakjl
Explorer
Explorer
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Registered: ‎07-20-2018

Hi @deepeshm ,

thank you for the reply and the explanation about the possible reasons that can trigger the error.

Our doubts are about the m_axis_h2c_tuser_err port behavior and how rarely it can be triggered.

Once the line is asserted, it stays asserted forever or just for one beat or for the duration of the entire transmitted packet?

It could became asserted in the middle of a packet or is an error consistent on the full packet (i.e. on all its beats)?

 

Thank you for the support, best regards.

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deepeshm
Xilinx Employee
Xilinx Employee
253 Views
Registered: ‎08-06-2008

Hi, How often or rarely it will get triggered depends on how error prone the system is. It will be active since the first beat that saw the error and will be asserted till the end of the packet. User is recommended to look at error registers and context for details on the reason behind the triggering of the signal. Let me know if you need further details.

Thanks.

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dsakjl
Explorer
Explorer
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Registered: ‎07-20-2018

Hi @deepeshm ,

thank you for the support.

Best regards.

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