QDMA: How to manually configure master read/write burst size
I'm evaluating the QDMA performance between host memory and UltraRAM in FPGA. I enabled my simple QDMA design on the Alveo U250 which is very similar to QDMA example desgin provided by Xilinx.
My performance results show that Read throughput (FPGA -> Host) achieves around 100Gbps but Write throughput (Host -> FPGA) is around 80Gbps even if I changed parameter such as queue size and packet size (transfered data size).
I tried to identify the root cause of this bottleneck and found that AXI Burst Size is different between Read (FPGA -> Host) and Write (Host -> FPGA). Attached screenshots show the Burst Size differences monitored by ILA.