04-27-2020 06:13 PM
In pg302 the description for soft_reset_n says it can be used to reset the DMA logic. It also says "only DMA logic". Can someone clarify what does this mean? What part of the QDMA IP does this signal reset? I understand that this doesn't reset PCIe hard block.
I have been trying to put this signal in use. But whenever I tried resetting QDMA using this signal, it never came back up properly. The C2H and H2C transfers doesn't seem to work after the reset. Registers hooked up to AXI-Lite master seems to work fine though.
Note that I am holding the reset for a minimum of 100 clock cycles as specified in pg302. So is there anything more to be done in the driver after the reset is de-asserted? Thanks.
04-28-2020 09:52 AM
Do you find the QDMA driver is staying linked to the IP in the FPGA after soft_reset_n is pulsed? Can you share the lspci log after pulsing soft_reset_n?
04-28-2020 11:16 PM
Yes, the driver is linked to the IP after soft_reset_n is disabled. I can see that in lspci, there are no changes/warnings.
But what I have seen using ILA is, c2h_cmpt_tready is stuck at 0 after the reset. c2h_tready seems to be fine though. For my use case I rely on the completion entry, but this won't work as tready is low.
(I would suspect h2c_tready is also stuck at 0 as I can't send any packets through H2C after the reset. I can't confirm this since I have not connected the relevant signals to ILA)
04-30-2020 03:42 AM