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661 Views
Registered: ‎12-03-2019

QDMA example design on Alveo U50

Hi,

I'm trying to get QDMA example working on the Alveo U50 using the Vivado flow with the IP integrator.

When trying to open the example design, I see the following errors in the console:

# generate_target open_example [get_ips qdma_1]
ERROR: [IP_Flow 19-3461] Value '4' is out of the range for parameter 'Pf0 Sriov Cap Initial Vf(PF1_SRIOV_CAP_INITIAL_VF)' for BD Cell 'qdma_1' . Valid values are - 0
ERROR: [IP_Flow 19-3461] Value '4' is out of the range for parameter 'Pf0 Sriov Cap Initial Vf(PF2_SRIOV_CAP_INITIAL_VF)' for BD Cell 'qdma_1' . Valid values are - 0
ERROR: [IP_Flow 19-3461] Value '4' is out of the range for parameter 'Pf3 Sriov Cap Initial Vf(PF3_SRIOV_CAP_INITIAL_VF)' for BD Cell 'qdma_1' . Valid values are - 0
INFO: [IP_Flow 19-3438] Customization errors found on 'qdma_1'. Restoring to previous valid configuration.
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to customize IP 'qdma_1'. Failed to apply user parameter values.
INFO: [Common 17-206] Exiting Vivado at Fri Jul  3 22:30:41 2020...
ERROR: [Common 17-69] Command failed: Unable to open example project; see previous messages.

 

Can someone please advise how to fix this ? I am trying to get a single function device example design and don't need SR-IOV functionality so it is disabled.

 

Seems like the example design has a bug ?

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Moderator
Moderator
576 Views
Registered: ‎02-16-2010

Hi @mateuszberezecki ,

Can you share the .xci file of the QDMA IP?

Thanks,

Srinadh

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550 Views
Registered: ‎12-03-2019

Hi@venkata ,

I'm attaching the .xci file for the QDMA IP

 

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Contributor
Contributor
414 Views
Registered: ‎07-10-2020

I am experiencing the same problem. Can you share the solution if you found one?

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Contributor
Contributor
390 Views
Registered: ‎07-10-2020

I have managed to find a solution.

Previously, I tried to open the example design in a block design. In this case, I couldn't open the example design.

When I open the example design in the IP catalog section, it works.

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Observer
Observer
161 Views
Registered: ‎09-22-2020

I was facing exactly the same problem in Vivado 2020.1 for target board in the family of Zynq Ultrascale+ devices, when trying to open an Example design for QDMA from instantiated Block Design.

Possible workaround is the solution provided by the TaekyungHeo, simply to open up the example design from the IP Integrator tab, without instantiating the IP in a Block Design.

Another workaround would be to make sure that all (in my case, 4) Physical Functions (PFs) are enabled in Capabilities tab when customizing the IP that is already instantiated in the Block Design.

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Observer
Observer
86 Views
Registered: ‎01-25-2013

I have a question , how to used uart in U250.

I download the U250 xci in xilinx ,and find the port is 

set_property -dict {PACKAGE_PIN BB20 IOSTANDARD LVCMOS12       } [get_ports USB_UART_RX       ]; # Bank 64 VCCO - VCC1V2 Net "USB_UART_RX"         - IO_T3U_N12_64
set_property -dict {PACKAGE_PIN BF18 IOSTANDARD LVCMOS12       } [get_ports USB_UART_TX       ]; # Bank 64 VCCO - VCC1V2 Net "USB_UART_TX"         - IO_L24N_T3U_N11_64
 
but when I use these two signals,the uart hadn't any signal.
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