08-06-2020 09:49 AM
we are using QDMA IP version 3 with patch AR73179 on Vivado 2019.2, and Xilinx
We configure the IP with two physical functions, PF0 and PF1, and enable
MSIx interrupts on both functions.
The QDMA documentation (pg302-v3.0, pag. 113) reports that there is a register
called "Config Block MSI Enable (0x14)", which indicates the interrupt enable
status of MSI and MSIx for each PF.
From DebugFS we see that this register contains the value 0x202, which basically
means that for PF0 and PF1 only the MSI interrupts are enabled and not the MSIx
ones. The expected value should be 0x101.
From Linux we correctly see MSIx interrupts.
Please, can you help us on this?
10-27-2020 07:10 AM - edited 10-27-2020 07:16 AM
anyone on this? Is there a patch to fix this issue?
Is it possible that the QDMA 3.0 documentation is wrong (page 113) ?