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dsakjl
Explorer
Explorer
583 Views
Registered: ‎07-20-2018

QDMA "Config Block MSI Enable" register

Hello everyone,

we are using QDMA IP version 3 with patch AR73179 on Vivado 2019.2, and Xilinx
driver (https://github.com/Xilinx/dma_ip_drivers/tree/master/QDMA/linux-kernel).

We configure the IP with two physical functions, PF0 and PF1, and enable
MSIx interrupts on both functions.

The QDMA documentation (pg302-v3.0, pag. 113) reports that there is a register
called "Config Block MSI Enable (0x14)", which indicates the interrupt enable
status of MSI and MSIx for each PF.

From DebugFS we see that this register contains the value 0x202, which basically
means that for PF0 and PF1 only the MSI interrupts are enabled and not the MSIx
ones. The expected value should be 0x101.

From Linux we correctly see MSIx interrupts.

Please, can you help us on this?

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dsakjl
Explorer
Explorer
405 Views
Registered: ‎07-20-2018

Hi all,

anyone on this? Is there a patch to fix this issue?

Is it possible that the QDMA 3.0 documentation is wrong (page 113) ?

Thank you.

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dsakjl
Explorer
Explorer
209 Views
Registered: ‎07-20-2018

Hi @deepeshm ,

as requested I report this possible bug to you.

Don't know if this is an implementation or documentation bug.

Best regards.

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