06-09-2020 09:16 AM
I am new to using the Xilinx DMA - pcie IP and would like some guidance on how to proceed. I have a task to provide a QDMA - PCIe design for the software engineers to exercise their code. Since I would like to start from the beginning from PCIe, to how the DMA in PCIe works I have gone through these references for background in this order:
1) How to create a PCI Express design in an ultrascale FPGA video (june 19, 2016)
2) xapp1286 - 7 series fpgasgen2 integrated block for pie to axi4-lite bridge
3) xtp227 - AC701 PCIe Design Creation
4) ug964 - AC701 Base TRD User guide - reading in progress
5) DMA for PCI Express (Sep 3, 2016) - today
Next to read:
5) xapp1171 - PCI Express Endpoint-DMA initiator subsystem
6) PG195 (v4.1) - DMA/Bridge Subsystem for PCI Express v4.1
7) PG302 (v3.0) - QDMA Subsystem for PCI Express v3.0
This is a lot to read to come up to speed on the DMA / PCIe and QDMA. Is this the correct path or is there a better list of appnotes to read?
Also, I saw in PG302 chapter 6 has these example designs mentioned, but I was not able to find the path to the Vivado project for them. Would you forward the link for them to me?
06-17-2020 08:10 PM
Thank you for the prompt reply.
The software people kept mentioning porting the QDMA drivers and Linux for 2 weeks so I got a little confused when I didn't see the QDMA IP available for Artix-7. I'm targeting the XDMA IP with the DMA/Bridge Subsystem v4.1 - PG195 with the examples in chapter 6 as a guide. I mentioned the Artix-7 doesn't support QDMA drivers too, so they've started looking into the XDMA drivers from Xilinx. By the way, are the drivers meant only for an x86 machine or will they port to an ARM MCU such as an i.MX6?
By the way, I might have a question about adding an AXI streaming interface on the read side of a fifo where the write side is non-AXI, but I'll search the forums first before asking. As background, I am using a fifo to receive adc data and streaming out to an MCU via DMA over PCIe.
Thanks again for the help,