cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
dsakjl
Explorer
Explorer
1,378 Views
Registered: ‎07-20-2018

QDMA user interrupts on PF1

Jump to solution

Hello,

we are using QDMA IP version 3 with patch AR73179 on Vivado 2019.2, and Xilinx
driver (https://github.com/Xilinx/dma_ip_drivers/tree/master/QDMA/linux-kernel).

We configured the IP with two physical functions, PF0 and PF1, and enable
MSIx interrupts on both functions.

Note that the QDMA logic is managed on PF0, while PF1 is basically used only
for user IRQs reception.

We developed a custom logic to generate IRQs on the QDMA user IRQ port.
The custom logic is connected to an AXI GPIO IP which is controlled by an
host user space application. We substantially use GPIOs to set the vector and
the function number of the IRQ, and to request the IRQ generation to our custom
logic.

With this configuration in place we are experimenting a strange issue.
Here is the steps we take:

1) flash the bitstream;

2) reboot the machine;

3) load the driver module;

4) call pci_enable_device() on PF1.
    All IRQs are correctly received on the host;

5) call pci_disable_device();

6) call pci_enable_device() on PF1.
    No IRQ is received on PF1 anymore;

7) after machine reboot we return to point 3.

On PF0 IRQs are correctly received anyway.
The same issue can be experimented on PF2 and PF3 when enabled.

Is there any reset that we should consider to solve this problem?

Please, can you help us on this?

1 Solution

Accepted Solutions
deepeshm
Xilinx Employee
Xilinx Employee
497 Views
Registered: ‎08-06-2008

Thanks for this. We have filed an internal request to investigate on this. 

As you reported you are not using the PF1 anymore, we will mark this thread as closed.

View solution in original post

7 Replies
dsakjl
Explorer
Explorer
1,201 Views
Registered: ‎07-20-2018

Hello everyone,

please, can we have support on this?

Thank you.

0 Kudos
liy
Xilinx Employee
Xilinx Employee
1,173 Views
Registered: ‎08-02-2007

The user interrupts are mapping using MSIX  table and  usr_irq_in_vec/ usr_irq_in_func

would you please check if the function number of PF1 test is mapping to the right MSIX table 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
dsakjl
Explorer
Explorer
1,134 Views
Registered: ‎07-20-2018

Hi liy,

thank you for the reply.

The QDMA MSIX table and PBA offsets are automatically configured as 0x10000
and 0x14000 on IP instantiation.
Reading from those offsets on Linux correctly returns the MSIX and PBA tables contents.
In particular, we see that the required MSIX vectors are correctly unmasked/masked
on driver modules loading/unloading both for PF0 and PF1.
So we can confirm that PF0 and PF1 map, respectively, to the right tables.

Consider that the problem we experiment only happens on PF1 when we unload the
relative driver module and reload it. After reloading, no IRQ is received on
PF1 anymore.

Please, do you have other suggestions?

Thank you.

0 Kudos
dsakjl
Explorer
Explorer
921 Views
Registered: ‎07-20-2018

Hi @liy ,

do you have other suggestions?

Thank you, best regards.

0 Kudos
dsakjl
Explorer
Explorer
886 Views
Registered: ‎07-20-2018

Hi @liy ,

is it possible that resetting the DMA part of the QDMA IP with the soft_reset_n port could solve the problem?

 

0 Kudos
dsakjl
Explorer
Explorer
527 Views
Registered: ‎07-20-2018

Hi @deepeshm ,

as requested I report this possible bug to you.

Best regards.

0 Kudos
deepeshm
Xilinx Employee
Xilinx Employee
498 Views
Registered: ‎08-06-2008

Thanks for this. We have filed an internal request to investigate on this. 

As you reported you are not using the PF1 anymore, we will mark this thread as closed.

View solution in original post