06-10-2019 06:55 PM
I have a question about "intx_msi_grant" output pin of AXI Bridge for PCI Express Gen3 Subsystem v3.0 block (PG194). Does the assertion of intx_msi_grant mean that the root port (the cpu) has received MSI, or just the core (the endpoint) received it and will send the interrupt message to cpu (root port) later? If it is later, when does the core send the MSI to report? Does it queue the requests? Thanks.
06-11-2019 04:51 AM
The 'intx_msi_grant' is asserted when the Endpoint IP has accepted an interrupt. For how this is handled please refer to the "Receiving Interrupts" section of PG194 from Page 79 in Chapter 3: Designing with the Core.
06-11-2019 08:43 AM
Hi @garethc , I read that section (Receiving Interrupts), it looks like it talks about the IP being configured/customized as root port. In my case, I use it as endpoint. Could you please elaborate on it or point me to the exact paragraph about it? I am concerned with sitatuation that multiple requests are asserted before intx_msi_grant is asserted. Of course I would like also like to understand the details. I will read the section more carefully to see if I can get a clearer picture. Thanks.
06-12-2019 03:17 AM
The intx/msi interrupt is a memory write (MWr) TLP and is sent out once there is enough credits. If there is an other outstanding TLP's they will be serviced first.
06-12-2019 06:11 AM
06-18-2019 03:34 AM
Some of these details are internal to our PCIe IP and I have engaged with the PCIe IP team to clarify this and I will get back to you with a valid response once I have it.
06-28-2019 06:02 AM
I have some feedback from PCIe IP team and they have confirmed that assertion of intx_msi_grants means that the PCIe IP has received the request but doesn’t gurantee that the PCIe IP has actually already sent it to the host, it can be done later or not at all in some cases such as (mask set or enable not set).
I hope this clarifies the behaviour for you.