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salahgamal
Adventurer
Adventurer
6,966 Views
Registered: ‎06-08-2011

Questions about axi_pcie in EDK 13.2?

Is the bridge include the PCIe core it self?

How to drive reset and clock for AXI interconnect?

When I build my EDK system there warring appear

 

WARNING:EDK - : Cannot determine frequency of INTERCONNECT_ACLK; generating TIG
   constraint for asynchronous clock-converter data pathways.

Checking port drivers...
WARNING:EDK:4180 - PORT: pci_exp_rxp, CONNECTOR: RXP - No driver found. Port
   will be driven to GND -
   /opt/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_v1_00_a/d
   ata/axi_pcie_v2_1_0.mpd line 222
WARNING:EDK:4180 - PORT: pci_exp_rxn, CONNECTOR: RXN - No driver found. Port
   will be driven to GND -
   /opt/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_v1_00_a/d
   ata/axi_pcie_v2_1_0.mpd line 223
WARNING:EDK:4181 - PORT: pci_exp_txp, CONNECTOR: TXP - floating connection -
   /opt/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_v1_00_a/d
   ata/axi_pcie_v2_1_0.mpd line 220
WARNING:EDK:4181 - PORT: pci_exp_txn, CONNECTOR: TXN - floating connection -
   /opt/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_pcie_v1_00_a/d
   ata/axi_pcie_v2_1_0.mpd line 221

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luisb
Xilinx Employee
Xilinx Employee
6,941 Views
Registered: ‎04-06-2010

I'd start off with this MHS.  It's a good working example and will show you the clocking structure.

 

hope this helps.

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salahgamal
Adventurer
Adventurer
6,928 Views
Registered: ‎06-08-2011

thanks

 

i used the clocking structure provided in system.mhs

after i build my system which include (axi4 and simple block RAM and axi_pcie bridge) and generate the bitstream the PC not identify the kit (virtex-6)

when i open system.ucf it empty Is this the problem?

 

the following warring appear in XPS

 

WARNING:ConstraintSystem:194 - The TNM
   'axi_interconnect_0_async_clock_conv_FFDEST', does not directly or indirectly
   drive any flip-flops, latches and/or RAMs and is not actively used by any
   referencing constraint.

WARNING:ConstraintSystem:194 - The TNM
   'axi_interconnect_0_async_clock_conv_FFDEST', does not directly or indirectly
   drive any flip-flops, latches and/or RAMs and is not actively used by any
   referencing constraint.

Checking Constraint Associations...
INFO:NgdBuild:981 - Could not find any associations for the following
   constraint:
       '<INST
   "axi_interconnect_0/*_converter_bank/*clock_conv_inst/*asyncfifo_*mem/*dout_i
   _???" TNM = "axi_interconnect_0_async_clock_conv_FFDEST";>
   [/home/sgamal/Salah/EDK_final/implementation/axi_interconnect_0_wrapper.ncf(6
   )]'
INFO:NgdBuild:981 - Could not find any associations for the following
   constraint:
       '<INST
   "axi_interconnect_0/*_converter_bank/*clock_conv_inst/*asyncfifo_*mem/*dout_i
   _????" TNM = "axi_interconnect_0_async_clock_conv_FFDEST";>
   [/home/sgamal/Salah/EDK_final/implementation/axi_interconnect_0_wrapper.ncf(7
   )]'
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "system.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:135 - Constraint <INST
   /system/EXPANDED/system/axi_interconnect_0/axi_interconnect_0\/mi_converter_b
   ank\/gen_conv_slot[0].clock_conv_inst\/s_axi_aresetn_resync<2>_inv1_INV_0 TNM
   = FFS:axi_interconnect_0_reset_resync>: No instances of type FFS were found
   under block
   "axi_interconnect_0/axi_interconnect_0/mi_converter_bank/gen_conv_slot[0].clock_conv_inst/s_axi_aresetn_resync<2>_inv1_INV_0" (type=INV).

WARNING:ConstraintSystem:135 - Constraint <INST
   /system/EXPANDED/system/axi_interconnect_0/axi_interconnect_0\/mi_converter_b
   ank\/gen_conv_slot[0].clock_conv_inst\/m_axi_aresetn_resync<2>_inv1_INV_0 TNM
   = FFS:axi_interconnect_0_reset_resync>: No instances of type FFS were found
   under block
   "axi_interconnect_0/axi_interconnect_0/mi_converter_bank/gen_conv_slot[0].clock_conv_inst/m_axi_aresetn_resync<2>_inv1_INV_0" (type=INV).

WARNING:ConstraintSystem:135 - Constraint <INST
   /system/EXPANDED/system/axi_interconnect_0/axi_interconnect_0\/si_converter_b
   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN
   V_0 TNM = FFS:axi_interconnect_0_reset...>: No instances of type FFS were
   found under block
   "axi_interconnect_0/axi_interconnect_0/si_converter_bank/gen_conv_slot[0].clock_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).

WARNING:ConstraintSystem:135 - Constraint <INST
   /system/EXPANDED/system/axi_interconnect_0/axi_interconnect_0\/si_converter_b
   ank\/gen_conv_slot[0].clock_conv_inst\/s_axi_aresetn_resync<2>_inv1_INV_0 TNM
   = FFS:axi_interconnect_0_reset_resync>: No instances of type FFS were found
   under block
   "axi_interconnect_0/axi_interconnect_0/si_converter_bank/gen_conv_slot[0].clock_conv_inst/s_axi_aresetn_resync<2>_inv1_INV_0" (type=INV).

WARNING:ConstraintSystem:135 - Constraint <INST
   /system/EXPANDED/system/axi_interconnect_0/axi_interconnect_0\/si_converter_b
   ank\/gen_conv_slot[0].clock_conv_inst\/m_axi_aresetn_resync<2>_inv1_INV_0 TNM
   = FFS:axi_interconnect_0_reset_resync>: No instances of type FFS were found
   under block
   "axi_interconnect_0/axi_interconnect_0/si_converter_bank/gen_conv_slot[0].clock_conv_inst/m_axi_aresetn_resync<2>_inv1_INV_0" (type=INV).

WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_0_reset_resync', does
   not directly or indirectly drive any flip-flops, latches and/or RAMs and is
   not actively used by any referencing constraint.

WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_0_reset_resync', does
   not directly or indirectly drive any flip-flops, latches and/or RAMs and is
   not actively used by any referencing constraint.

WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_0_reset_resync', does
   not directly or indirectly drive any flip-flops, latches and/or RAMs and is
   not actively used by any referencing constraint.

WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_0_reset_resync', does
   not directly or indirectly drive any flip-flops, latches and/or RAMs and is
   not actively used by any referencing constraint.

WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_0_reset_resync', does
   not directly or indirectly drive any flip-flops, latches and/or RAMs and is
   not actively used by any referencing constraint.

Done...

Processing BMM file "system.bmm" ...

WARNING:Data2MEM:53 - File 'system.bmm' was empty or had no BMM content.

WARNING:Par:288 - The signal
   axi_interconnect_0/axi_interconnect_0/si_converter_bank/gen_conv_slot[0].clock_conv_inst/gen_conv_read_ch.gen_ar_async.asyncfifo_ar/fifo_
   gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD_D1_O has no load.  PAR will not attempt to
   route this signal.

 

 

 

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luisb
Xilinx Employee
Xilinx Employee
6,921 Views
Registered: ‎04-06-2010

Give this UCF a try:

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salahgamal
Adventurer
Adventurer
6,904 Views
Registered: ‎06-08-2011

when i use UCF file this error appear in xps

 

ERROR:ConstraintSystem:58 - Constraint <INST
   "*/PCIe_Diff_Clk_I/USE_IBUFDS_GTXE1.GEN_IBUFDS_GTXE1[0].IBUFDS_GTXE1_I" LOC =
   IBUFDS_GTXE1_X0Y6;> [system.ucf(9)]: INST
   "*/PCIe_Diff_Clk_I/USE_IBUFDS_GTXE1.GEN_IBUFDS_GTXE1[0].IBUFDS_GTXE1_I" does
   not match any design objects.
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1

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salahgamal
Adventurer
Adventurer
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Registered: ‎06-08-2011

thanks my problem is solved and the pc identify kit 

 

 

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