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ccmake23
Adventurer
Adventurer
9,417 Views
Registered: ‎10-28-2011

Quick method to create a PCIe link for board validation

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Hi there: I'm building a FPGA board as a platform for ASIC team in my company. The FPGA chip is XC7VX690T-2FFG1927C. In my design,​ there are 8 PCIe Endpoints(X1),​ which are implemented in 8 MGT banks. To me,​ I need a quick method to createt 8 PCIe EP design for initial board validation. I think PHY link validation will be good enough for me(Host PC recognizes these 8 EPs with PCIe tool,​ with different DID and VID). So my question is,​ is there any ready-to-use design for my application?​ I checked the document about PCIe IP core,​ but I need to implement 8 EPs at the same time. And,​ I don't know how to put the core in the FPGA,​ and create the UCF file. Is there any reference that I can refer to ?​ I just want to test the link path on PCB board, and don’t need to deal with the design in the FPGA chip. (Can I just put the IP core in a design without writing extra verilog code? I noticed that the template of the core contains lots I/O pins. I just need 1 PCIe lane, REFCLK, RESET signals interfacing with HOST PCIe slot. Can I leave all the internal signals unconnected?) Thanks a lot for the help! :)
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liy
Xilinx Employee
Xilinx Employee
16,390 Views
Registered: ‎08-02-2007

Hi 

The PCIe core of Xilinx is hard core  and  there are only up to 4 cores in one FPGA

It looks like you need to use  a soft core 

One possible solution is that you can create a hardcore, open the example design, all the necessary UCF/xdc files are included .You can replace the hardcore with your own softcore directly

repeate this for 8 times but you will need to modify the ucf/xdc for the locations of Reset and clock pins

 

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liy
Xilinx Employee
Xilinx Employee
16,391 Views
Registered: ‎08-02-2007

Hi 

The PCIe core of Xilinx is hard core  and  there are only up to 4 cores in one FPGA

It looks like you need to use  a soft core 

One possible solution is that you can create a hardcore, open the example design, all the necessary UCF/xdc files are included .You can replace the hardcore with your own softcore directly

repeate this for 8 times but you will need to modify the ucf/xdc for the locations of Reset and clock pins

 

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ccmake23
Adventurer
Adventurer
9,345 Views
Registered: ‎10-28-2011

Hi Liy: Thanks a lot for your reply. I think I might use the example design provided by the IP core generator and create 8 times for my board, in order to test my 8 ports. I found a document -- XTP044 (ML605 PCIe x8 Gen1 Design Creation), which seems OK for my testing. I tried to add the PCIe core with coregen, and create the .xco file in ISE. But I'm not sure what I have to do next. In page 20 of this document, it uses the batch file to create the bit file, but I want to use the GUI in ISE tool, and I need to modify the UCF file for my board's pinout. What files should I add into the ISE sources? All the files in "example_design" folder? Or any other sources? I wish that I can generate the programming file after adding these files in ISE tool. Thanks a looooooooot! :)

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kotir
Scholar
Scholar
9,325 Views
Registered: ‎02-03-2010

hi David,

 

I think we have already web case open for this.

Please continue to respond to it so that you doubts get clear.

 

Regards,

Koti Reddy

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ccmake23
Adventurer
Adventurer
9,298 Views
Registered: ‎10-28-2011

Hi Koti:

 

Yes, we can close this thread.

Thanks.

 

David

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