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Visitor
Visitor
3,879 Views
Registered: ‎08-31-2010

Read/Write to endpoint works in one PCIe slot but not another

I am using a supermicro X8DA3 motherboard with a x4 endpoint device.  When I plug the x4 endpoint device into slot #2 which is a PCIe x4 gen1 connected to the southbridge(Intel ICH10R), I can read/write to the address range 0x00 to 0xFF correctly.  If I move the card to slot #3 which is a PCIe x16 GEN2 slot connected to the north bridge(Intel 5520), I can read/write correctly from 0x00 to 0x7F but address 0x80 to 0xFF return zeros.  The read errors repeat every 0x100(i.e 0x180 to 0x1FF fails)  All writes are 3-DW headers, with data length 1 and all reads are 3-DW headers no data (length 1).  I can look at the traffic with Chipscope and in both slots the data packets look identical except for the base address, and source,dest id's.

 

Any ideas?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2008

Which device are we talking about V5 or V6?

When you try to access 0x80 to 0xFF, do you see the corresponding memory read TLP appearing at the trn interface i.e. between the user application and the core, in Chipscope? If you do, do you see the corresponding completion going out from the user application to the core?

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Visitor
Visitor
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Registered: ‎08-31-2010

The device is a V5SX50T.  Yes I can see all the packets in Chipscope.  I can see the write packet, read packet, and completion packet.  When I compare the packets between the good slot and the bad slot they are identical except for BAR, and the id's

 

Thanks

Bill

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