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Observer
Observer
9,515 Views
Registered: ‎09-01-2014

Receiving Completion Timeout from pcie3_7x_0_pcie_3_0_7vx for Bus Mastering MEM_RD request

It's coming back with 'request_completed=1'

 

Here is an ILA dump of the RC data coming back:

 

   Tag__63.....32__31......0

   --------------------------
     0__0000_0000__4000_9000
     1__0000_0000__4000_9000
     2__0000_0000__4000_9000
     3__0000_0000__4000_9000
     4__0000_0000__4000_9000
     5__0000_0000__4000_9000
     6__0000_0000__4000_9000
     7__0000_0000__4000_9000
     8__0000_0000__4000_9000
     9__0000_0000__4000_9000
     A__0000_0000__4000_9000
     B__0000_0000__4000_9000
         ...and so on...
    1F__0000_0000__4000_9000

 

error-code.PNGerror-code1.PNG

 

What could be causing such behavior?

  Any insight and lead counts!

 

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Highlighted
Observer
Observer
9,493 Views
Registered: ‎09-01-2014

It might be of interest to mention that READY returned by RQ bus goes to 0 on 40th MEM_RD request (last Tag is 0x27 and Tags start from 0)

 

Complete image of RQ bus:

RQ-bus1.PNG

 

 

RQ bus zoom in around first MEM_RD request (Tag=0):

RQ-bus2.PNG

 

 

RQ bus zoom in around last MEM_RD request (Tag=0x27):

RQ-bus3.PNG

 

 

 

 

Complete image of RC bus:

RC-bus1.PNG

 

 

RC bus zoom in around first MEM_RD Completion Timeout packet (Tag=0):

RC-bus2.PNG

 

RC bus zoom in around last MEM_RD Completion Timeout packet (Tag=0x1F):

RC-bus3.PNG

 

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Highlighted
Observer
Observer
9,470 Views
Registered: ‎09-01-2014

Reducing the number of pending Requests (which avoids ~Ready from the core) has not helped remove Completion Timeouts. Here is the RQ timing with no more than 8 pending requests:

RQ-bus4.PNG

It clearly shows that 'valid' from RQ is now constantly 1.

It also shows that the RC Completion Timeout must be coming more than 1024 cycles after the first RQ (as my logic is waiting for the 1st Completion to send the 9th Request.

 

I'm planning to build a deeper ILA, one that captures both RQ and RC together. With that, I should be able to see something like the High Performance case in the cool Altera diagram and description, except that I'll have 8 instead of 4 initially-queued up RQs. Note that the max MEM_RD request size in my case is 512bytes, not the 4kbytes that the PCIE spec allows.

altera.PNG

 

 

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Highlighted
Observer
Observer
1,526 Views
Registered: ‎03-20-2009

Hi chili.chips,

 

How did you managed to fix the completion timeout issue? I am getting this issue even when only one Memory Read request is sent to the core. But the core works well in hardware for Memory Writes. Could you please help me on this?

 

Completion Timeout.PNG

 

Thanks in advance.

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