12-10-2014 12:44 AM
It's coming back with 'request_completed=1'
Here is an ILA dump of the RC data coming back:
...and so on...
What could be causing such behavior?
Any insight and lead counts!
12-10-2014 01:32 PM
It might be of interest to mention that READY returned by RQ bus goes to 0 on 40th MEM_RD request (last Tag is 0x27 and Tags start from 0)
Complete image of RQ bus:
RQ bus zoom in around first MEM_RD request (Tag=0):
RQ bus zoom in around last MEM_RD request (Tag=0x27):
Complete image of RC bus:
RC bus zoom in around first MEM_RD Completion Timeout packet (Tag=0):
RC bus zoom in around last MEM_RD Completion Timeout packet (Tag=0x1F):
12-11-2014 09:43 AM
Reducing the number of pending Requests (which avoids ~Ready from the core) has not helped remove Completion Timeouts. Here is the RQ timing with no more than 8 pending requests:
It clearly shows that 'valid' from RQ is now constantly 1.
It also shows that the RC Completion Timeout must be coming more than 1024 cycles after the first RQ (as my logic is waiting for the 1st Completion to send the 9th Request.
I'm planning to build a deeper ILA, one that captures both RQ and RC together. With that, I should be able to see something like the High Performance case in the cool Altera diagram and description, except that I'll have 8 instead of 4 initially-queued up RQs. Note that the max MEM_RD request size in my case is 512bytes, not the 4kbytes that the PCIE spec allows.
01-21-2018 09:46 PM
How did you managed to fix the completion timeout issue? I am getting this issue even when only one Memory Read request is sent to the core. But the core works well in hardware for Memory Writes. Could you please help me on this?
Thanks in advance.