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Contributor
Contributor
141 Views
Registered: ‎06-05-2017

Request fix for AXI PCIe Bridge Gen 3

The AXI Bridge for PCI Express Gen 3 has a rather obscure and annoying feature that doesn't seem to be documented (or if it is, it's not clear):

Dynamic Address Translation for the AXI BARs only works when the C_AXIBAR2PCIEBAR_* registers are a multiple of the AXI2PCIE BAR aperture size. Thus, if AXI BAR0 is given an address space of 8MiB, a system buffer must also be 8MiB aligned.

It would be nice if this was either made more obvious, or fixed. Thanks!

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Xilinx Employee
Xilinx Employee
56 Views
Registered: ‎08-06-2008

Re: Request fix for AXI PCIe Bridge Gen 3

We provide examples in PG194 (on page 66 - July 2019 version). Also, the document below provides more information on address translation.

https://www.xilinx.com/support/answers/65062.html

I think your concern is addressed in the above sections.

Please suggest if we need more clarity in the document. Also, suggest where in the document would you like more information added. A specific example would be helpful. We try to make our documents as clear as possible. Feedback like these would be very valuable.

Thanks.

 

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