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Adventurer
Adventurer
289 Views
Registered: ‎05-27-2008

Root complex - Use of BAR0

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Hi,

We are currently trying to integrate the core PCIe to AXI to our Zynq (ZC706 EV board) design. In our design, the core is configured as Root Complex. When customizing it, we noticed that it is possible to configure its BAR0 and its translation mechanism to/from AXI (PCIE:BARS and AXI:BARS).

Could you please explain the purpose of having a BAR for the Root Complex ? Is it for the PS to allocate a memory space for its own PCIe interface management?

Many thanks in advance,

Nicolas Boucquey

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Moderator
Moderator
225 Views
Registered: ‎02-16-2010

Re: Root complex - Use of BAR0

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Hi @deltaxlx 

Please check page 81 of PG194 for information about Root Port BAR

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Moderator
Moderator
226 Views
Registered: ‎02-16-2010

Re: Root complex - Use of BAR0

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Hi @deltaxlx 

Please check page 81 of PG194 for information about Root Port BAR

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Don't forget to reply, give kudo and accept as solution
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View solution in original post