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Visitor
Visitor
9,326 Views
Registered: ‎10-18-2011

Sending an MSI over PCIe from axi_pcie

Hi,

I'm based on the AR43371 design (http://www.xilinx.com/support/answers/43371.htm) and I would like to add the possibility to send an MSI over the PCIe to the Host CPU (not the microblaze), but I don't understand how to achieve that goal.

In fact, I would like to drive the axi_cdma_0 and axi_cdma_1 from the Host CPU (map their registers inside PCI BARs) and receive MSI 0 when axi_cdma_0 is done and MSI 1 when axi_cdma_1 is done (for example).

Inside the documentation (ds820_axi_pcie.pdf), I read that I can send an MSI with the INTX_MSI_Request signal, but how can I select the associated message number itself?

Thanks in advance.

Best regards.

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11 Replies
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Visitor
Visitor
9,318 Views
Registered: ‎10-18-2011

I think this is a limitation of the axi_pcie compared with the native pcie block: only one vector, no multiple vectors.

Could anyone confirm this assertion?

Also, could anyone point out what are the other limitations of the axi_pcie compared with the native pcie block?

In terms of achievable bandwidth?

In terms of other functionalities?

Thanks.

Best regards.

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Xilinx Employee
Xilinx Employee
9,314 Views
Registered: ‎08-06-2008

Yes axi_pcie only supports one vector.

There isn't any document as such that compares between the two cores but you could take a look at the data sheet of the cores and compare the provided list of features.

 

Thanks,

DMS

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Visitor
Visitor
9,310 Views
Registered: ‎10-18-2011

Thanks for your answer.

I was asking if anyone knows about other limitations because the mono-vector limitation is not written inside the lastest axi_pcie product specification.

Best regards.

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Adventurer
Adventurer
9,288 Views
Registered: ‎06-08-2011

i have the same Question about how to send axi_DMA  inerrupt througth axi_pci without the use of microblaze processor 

how can i start such this issue?

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Visitor
Visitor
9,278 Views
Registered: ‎10-18-2011

I think the best method is to create an axi_intc to control your different interrupt sources and connect the Irq output port of the axi_intc to the INTX_MSI_Request input port of the axi_pcie.

Note that you can bypass the use of the axi_intc and connect your interrupt sources directly to the INTX_MSI_Request input port of the axi_pcie.

For the axi_intc, I think the output must be level for INTX and edge for MSI.

Could anyone confirm?

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Adventurer
Adventurer
9,269 Views
Registered: ‎06-08-2011

thanks araquirit for your replay
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Observer
Observer
4,833 Views
Registered: ‎02-26-2016

I am currently trying to do the same: using an AXI INTC to trigger MSI interrupts using the AXI PCIe endpoint bridge.

 

Usually AXI INTC is used with Microblaze-based systems. But it is possible to remap most of the ports to the AXI PCIe bridge.

 

  • Use fast interrupt method in AXI INTC
  • Connect IRQ output of AXI INTC to 'INTX_MSI_Request' of AXI PCIe bridge
  • Connect the 'interrupt_address' using a slice IP to the 'MSI_Vector_Num' input
  • Connect the 'INTX_MSI_Grant' signal to the 'processor_ack'

At the last point, I ran into a problem. 'processor_ack' expects a 2 bit vector. 'INTX_MSI_Grant' is only a single bit vector. :-(

 

AXI_PCIe_INTC.png

 

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4,501 Views
Registered: ‎04-02-2015

Hi,I have the same question as you.About axi intc IP core used by your diagram,do you successfully test this and how?

 

hope your response

 

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Observer
Observer
4,455 Views
Registered: ‎02-26-2016

I solved the problem adding a wrapper around axi_intc which emulates the interrupt handshaking which is expected by the PCIe AXI bridge.

 

I attached my packaged IP. Have a look at the VHDL code for the handshaking.

 

Please leave a Kudo if it works for you :-)

 

Highlighted
2,353 Views
Registered: ‎04-02-2015

Thanks for you response.I noticed your VHDL handskake code require must be MSI interrupt.But in my application,
I used legacy interrupt.I also used signal INTX_MSI_Grant output form axi bridge IP core as a handshake signal.
But I don't know how many cycle that INTX_MSI_Requst signal should be keep assert.Do you have any idea?

 

 

inter.png

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Visitor
Visitor
1,649 Views
Registered: ‎02-04-2018

Hello,

I was wondering if you could help me.  I am having the same issue and I implemented your solution, but I still cannot see any interrupts at the host.  I have 2 interrupts going into the INTC ip core, but the host only registers 1 MSI interrupt.

Can you provide more details on how you had the INTC and PCIE core setup?

Did you have any code running on the Microblaze to support the interrupts?

 

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