Set PCIe bridge address translation to custom core memory space.

[jmonteiro-dme]

Hi,

Is it possible to set the PCIe PLB Bridge address translation to a custom core address space instead of a free region in memory? Will i be able to write directly to the custom core address space through PCIe?

Best,

JM

[kennyj · Accepted solution]

Hi JM,

Yes, you can set it to anything in the 4GB address space of the PLB bus. You set it at build time via the MHS by setting the C_PCIBAR2PIFBAR_x parameter

For future questions regarding the PCIe PLB bridge you will get better detailed responses by posting to the Embedded Processing Forum.