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Explorer
Explorer
3,123 Views
Registered: ‎05-15-2009

Set PCIe bridge address translation to custom core memory space.

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Hi,

 

Is it possible to set the PCIe PLB Bridge address translation to a custom core address space instead of a free region in memory? Will i be able to write directly to the custom core address space through PCIe?

 

 

 

Best,

JM

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Xilinx Employee
Xilinx Employee
3,653 Views
Registered: ‎02-01-2010

Re: Set PCIe bridge address translation to custom core memory space.

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Hi JM,

 

Yes, you can set it to anything in the 4GB address space of the PLB bus. You set it at build time via the MHS by setting the C_PCIBAR2PIFBAR_x parameter

 

For future questions regarding the PCIe PLB bridge you will get better detailed responses by posting to the Embedded Processing Forum.

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Xilinx Employee
Xilinx Employee
3,654 Views
Registered: ‎02-01-2010

Re: Set PCIe bridge address translation to custom core memory space.

Jump to solution

Hi JM,

 

Yes, you can set it to anything in the 4GB address space of the PLB bus. You set it at build time via the MHS by setting the C_PCIBAR2PIFBAR_x parameter

 

For future questions regarding the PCIe PLB bridge you will get better detailed responses by posting to the Embedded Processing Forum.

View solution in original post

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