07-25-2019 07:12 AM
Hello. I'm working on connecting two pieces of Xilinx IP to test an FPGA. Both are the Xilinx AXI-PCie IP, version 2.9 using Vivado 2018.3. I am able to get the link to establish between the root port and the endpoint. But when when I send an AXI read/write on the S_AXI_* bus of the root port, I don't see any movement in the endpoint. I don't get any errors also on the *resp signals. If I use the model root port that's generated when I choose "open example design" for the endpoint IP, I am able to perform reads and writes to the endpoint.
I haven't been able to find any resources about setting up the root port IP to talk to the endpoint. I've tried mimicing what happens with the example model root port from the endpoint TB (which the root port is not the same IP) but with no success. I've tried with and without the BAR translations. I don't have a PCIe analyzer in my Cadence environment to see why the model root port is working and not the root port IP. Just wondering if anyone has tried hooking up these two IP's and/or if there's any examples or resources out there. Thank you in advance
08-05-2019 12:43 AM
did you set the Bus Master Enable bit in Root port's Command reg?
You can try to read the Command Reg from root port and see the bit. if it is 0, you need to set it before the Root port can send out packets to the bus.
08-06-2019 05:14 AM
Thank you for the reply.
I did write to that register, but reading it back I only see a status bit, not any of the command bits I set.
The C_BASEADDR is 0, so there should be no offset to the PCIe config reg from what I read in the spec. Do you know what could cause the descrepancy between the write and the read?