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Observer
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Registered: ‎09-29-2015

Shared Logic PCIe/7_Series_FPGAs_Transceivers

1) Context definition
- I'm using an ARTIX-7 FPGA (XC7A35TCSG325-1LI).
- As shown in 1a schematic, I'm using 1 GTP quad which has 4 available channels. 2 are used, the first on (X0Y0) for 1 PCIe to use a 1 lane 2.5GT/s PCIe and the second one (X0Y1) to output HD_SDI 720p30.
- IP's used are "7 Series FPGAs Transceivers Wizard (3.6)" (TX only) for SDI and the "AXI Memory Mapped To PCI Express (2.9)" for PCIe.
--- 7 Series FPGAs Transceivers shared logic is configured in mode "Include Shared Logic in example design".
--- PCIe IP is in a block design which shared logic is configured in "Include Shared Logic (Transceiver GT_COMMON_ in example design)" | Endpoint mode.
----- This is done to be able to configure the GTPE2_COMMON part.
- I got and reconfigured the common part GTPE2_COMMON (see attached gtpe2_common.txt) in order to the have the 148.5MHz MGTREFCLK0 for SDI driving the PLL1 (see schematic 1b) and the 100.0MHz MGTREFCLK1 for PCIe driving the PLL0 (see 1d schematic).
- I've read the following documents :
--- https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf
--- https://www.xilinx.com/support/documentation/ip_documentation/gtwizard/v3_6/pg168-gtwizard.pdf
--- https://www.xilinx.com/support/answers/51369.html
--- https://www.xilinx.com/support/answers/62530.html
--- https://forums.xilinx.com/t5/Serial-Transceivers/SGMII-and-SFP-in-same-quad-sharing-GTXE2-COMMON-VC-707/m-p/1072925

2) Issue description :
Once PCIe IP is configured, I have to drive following ports :
A DRP (Dynamic reconfiguration Port) interface (qpll_drp_clk[1:0], qpll_drp_crscode[11:0], qpll_drp_done[1:0], qpll_drp_fsm[17:0], qpll_drp_gen3[1:0], qpll_drp_ovrd[1:0], qpll_qplld[1:0], qpll_drp_reset[1:0], qpll_drp_rst_n[1:0], qpll_drp_start[1:0], qpll_qplllock[1:0], qpll_qplloutclk1:0], qpll_qplloutrefclk[1:0], qpll_qpllreset[1:0])
(see 2a shematic) for which I don't find information.
I first thought that qpll_qplllock[1:0], qpll_qplloutclk1:0], qpll_qplloutrefclk[1:0], qpll_qpllreset[1:0], qpll_qplld[1:0] ports concerned PLL0LOCK, PLL1LOCK, PLL0OUTCLK, PLL1OUTCLK PLL0OUTREFCLK, PLL1OUTREFCLK, PLL0RESET, PLL1RESET, PLL0PD, PLL1PD GTPE2_COMMON I/Os.
However when i generated the PCIe example design (see 2b schematic), I noticed that 2 GTPE2_COMMON are instanciated, connected to their DRP sub-module, and that the 2 GTPE2_COMMON signals are concatenated to drive PCIe IP (ie : QPLL_DRP_FSM[8:0] of gt_common_i_0 and gt_common_i_1 are used to create qpll_drp_fsm[17:0]).

Then, I don't see how driving PCIe logic, knowing that I'm using only one GTP quad:

- Maybe instanciate only one GTPE2_COMMON, extract and drive the sub-module qpll_drp and (ie for qpll_drp_fsm[17:0], drive only the [8:0] to QPLL_DRP_FSM[8:0] and others stuck at '0' ?
--- I've been told that if I don't use, sub-module qpll_drp could be ignored (not instanciated) and PCIe drp I/Os can be open/stuck_at_0 ?
- For PCIe signals : qpll_qplllock[1:0], qpll_qplloutclk1:0], qpll_qplloutrefclk[1:0], qpll_qpllreset[1:0], qpll_qplld[1:0], can I do the same thing, by driving only GTPE2_COMMON PLL0 I/Os on bit 0 and let bits 1 to open/stuck_at_0 or should I also drive them using GTPE2_COMMON PLL1 I/Os ?

Any help will be appreciated. Thanks.

1a.png
1b.png
1d.png
2a.png
2b.png
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