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brent.aandd
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Registered: ‎02-15-2018

Sharing Transceiver QPLL between PCIe and Ethernet PCS/PMA

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I am using a Zynq FPGA with a single transceiver bank. I am attempting to instantiate a PCIe Core and an Ethernet PCS/PMA on the same transceiver bank. Based on the CPLL table (ug476 Table 2-11), it appears that if I am using a 125MHz clock coming into the transceiver bank, I should be able to use a single QPLL to generate 125MHz and then the CPLL’s for each channel can take care of the rest. For reference, I included a diagram. Is this correct?

 Shared_QPLL.png

Here is my setup:

-PCS/PMA is configured to allow shared logic in the core

-AXI Memory Mapped PCIe is configured to Include Shared Logic (Transceiver GT_COMMON) in example design

 

Unfortunately, when I do this the externalized interfaces do not match up. After further digging into the generated code, I see that the PCIe is externalizing a DRP interface along with the QPll logic.

 

Am I doing this correctly? If so, what is the best way to connect the externalized signals between the two cores?

 

Thanks!

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brent.aandd
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Registered: ‎02-15-2018

I have found a solution that appears to generate a PCIe Core with no QPLL. Here are the steps:

-Select generate gt_common in the example design for the PCIe core

-Generate example design from core

-Comment out the 2 resulting gt_common blocks in the example code

-Verify pinout and board constraints

 

Core is detected by OS with the above design. My understanding, however, is that the BIAS_CFG is not set corectly in this case and that I will see a higher BER. AR43339 

 

Once I paste the modified example code into my design which already contains a PCS/PMA Core with QPLL in the same Quad, the BER problem should be fixed.

 

 

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venkata
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Registered: ‎02-16-2010
The diagram is incorrect. QPLL output cannot drive CPLL.

Can you try the other way?
-PCS/PMA is configured to allow shared logic in the example

-AXI Memory Mapped PCIe is configured to Include Shared Logic (Transceiver GT_COMMON) in core
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brent.aandd
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Registered: ‎02-15-2018

Thank you, I miss-read the transceiver guide about the QPLL and CPLL.

 

I tried your solution, but the ports created did not match up. I did however have a couple additional questions:

 

-Do the cores require both a QPLL and CPLL? I was thinking this may be required to provide an independent clock on the TX and RX. Maybe for clock recovery?

 

-Also, can I actually share clock logic between the two cores when they are transmitting at different frequencies (100MHz PCIe vs 125MHz GigE).

 

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venkata
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Registered: ‎02-16-2010
For 7-series designs, QPLL instantiation needs to be in the design even if it is not used. Please check AR#43339
https://www.xilinx.com/support/answers/43339.html

For this reason, I have asked to use shared logic in core option for only one core. QPLL will be part of this core. If the other is generated with "shared logic in example" option, then QPLL will not be present in that IP.

Which logic is shared between the two IPs? Is it part of your design outside of the IP's?
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brent.aandd
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Thank you for explaining. 

 

There is not much shared outside of the IP Cores. They do not even need to share a reference clock since I have a second reference clock available.

 

Currently the Ethernet is attached to the Zynq processing core's built in MACs. The PCIe will likely attach to the processing core via the AXI interface.

 

So that you can see what I am having trouble with, once I configured the PCIe to provide shared logic and the PMA/PCS to put the shared logic in the example design, I ended up with several ports which I did not know how to connect. I have highlighted them below.

Capture.PNG

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venkata
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Registered: ‎02-16-2010
The connections shown seems wrong. userclk/userclk2 should be shared between two identical cores. Please do not connect them from PCIe to ethernet.

Since QPLL is not used with both the IPs, the connections between the two IP's does not impact any functionality.

Please remove the connection to mmcm_locked on ethernet IP. You will need to instantiate a clocking wizard and configure it similar to Ethernet IP example design.

I recommend generating IP example design for both PCIe and Ethernet to understand how the ports at the IP interface needs to be connected
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brent.aandd
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Registered: ‎02-15-2018

I have found a solution that appears to generate a PCIe Core with no QPLL. Here are the steps:

-Select generate gt_common in the example design for the PCIe core

-Generate example design from core

-Comment out the 2 resulting gt_common blocks in the example code

-Verify pinout and board constraints

 

Core is detected by OS with the above design. My understanding, however, is that the BIAS_CFG is not set corectly in this case and that I will see a higher BER. AR43339 

 

Once I paste the modified example code into my design which already contains a PCS/PMA Core with QPLL in the same Quad, the BER problem should be fixed.

 

 

View solution in original post

toblerone90
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Registered: ‎05-15-2018

Hi,

as addition I want to share my solution. I had the same issue using 2x GbE + 1x PCIe on ZYNQ xc7z015clg485-2. (PCS/PMA blocks are crossover connected to form a GBE bridge)

1) Configure the PCS/PMA to include shared logic in core

2) Configure the second PCS/PMA to include shared logic in example design

3) Configure the AXI PCIe Core to include GT_COMMON in example design (Include Clocking in Core)

4) Use concats to connect the PPL outputs from the PCS/PMA to PCIe-AXI QPLL signals

5) Wire everything up as shown in picuture.

6) Both cores need to operate at 125 MHz frequency from the Transceiver Refclk

7) Works for Vivado 2018.3

Regards

Martin

 

pcie_eth_zynq7015.PNG
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