cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
eiownlee
Observer
Observer
922 Views
Registered: ‎03-26-2018

Some problems about flow control

 

     I have met some problems using PCIE integrated block v1.3 gen 3.0 recently.User logic transmit data to host by the way of dma, and the ports of cfg_fc_ph and cfg_fc_pd are used to control the data flow. The port cfg_fc_sel is set to 3'b100, and the initial value of cfg_fc_ph and cfg_fc_pd are 60 and 246 respectively. It's about 3.75k byte posted transaction fifo in the pcie core for transmitter. Here is my first problem : How can I set the value of cfg_fc_ph so there will be 16k byte posted transaction fifo?

    With the user logic transmitting data to host, the value of cfg_fc_ph and cfg_fc_pd will decrease accordingly. And the value will increaseafter the data pass through the pcie core, if all the data pass by, the value will recover to the init value. Here is a problem: The signal of ready keeps valid, and the port of cfg_fc_ph and cfg_fc_pd keep above 0,but the value won't return to 60 and 246, for example ,sometimes they are 54 and 150 . And there is another problem : The data seems pass the pcie core more and more slowly, for the value of cfg_fc_ph and cfg_fc_pd need more clock periods to change.

    So, thank you very much for help.

0 Kudos
3 Replies
liy
Xilinx Employee
Xilinx Employee
882 Views
Registered: ‎08-02-2007

cfg_fc_pd and other fc signals are usually used as output to monitor the FC, not input 

after the core is generated the value of credits of the core is fixed 

Some core may have "performance" in the GUI tab to select the init BRAM used for Credits but for most of the Cores , user can not change the value

cfg_fc_ph and cfg_fc_pd  usually take about 2 clock cycles to change  and it is expected.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
eiownlee
Observer
Observer
864 Views
Registered: ‎03-26-2018

 

    The signal "cfg_fc_pd" and other fc control are turely output, which I use to monitor the FC. Maybe I should represent my problems more clearly.

     1. The initial pd credits available are 246, 3.75KB, while the initial pd credits available are 512, 8KB. I wonder why the 8KB fifo are used at the power up

     2. The user logic sends a memory write to host, the data length is 256B. From the head of rq packet to the pd/ph change the value, it takes 72 clock periods. And it takes more and more clock periods with the logic sending data to host.

     3. The dma write may not work sometime for the host can't receive the data. I have checked the cfg_local_error and AER registers, and found the cfg_local_error_out= 10010b, which is “ unexpected completion received” in pg213. What does it mean?

 

0 Kudos
bethe
Xilinx Employee
Xilinx Employee
809 Views
Registered: ‎12-10-2013

Hi @eiownlee,

 

This means that the block has had a completion pushed in to the CC interface for which it does not have a corresponding outstanding request, or a data type "completion" was used on an unexpected interface (like the RQ).   I would recommend checking the formatting of your packets around that time. 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------