I use the PCIE Integrated Endpoint Block in a Spartan-6 device.
The clock ports MGTCLK and USERCLK are connected via a BUFG to the outputs of a PLL_BASE as generated by the coregen.
If I use BUFGCE instead of BUFG I get following message:
[PhysDesignRules 2214] Unexpected PCIE configuration. The s6_pcie_v2_4_0_i/PCIE_A1_inst Spartan-6 Integrated Block's USERCLK and MGTCLK inputs must each be sourced by different outputs, going through a BUFG, from the same PLL.
[Pack 1642] Errors in physical DRC.
Because I use both clocks for my FPGA logic I'd like to use BUFGCE to properly startup after configuration. See